CVS commit: src/sys/arch/x86/include

["SAITOH Masanobu" <msaitoh%netbsd.org@localhost>]

Module Name:    src
Committed By:   msaitoh
Date:           Mon Mar 12 07:35:45 UTC 2018

Modified Files:
        src/sys/arch/x86/include: cacheinfo.h

Log Message:
 AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.


To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.