CVS commit: src/sys/arch/sgimips/mace

["Jared D. McNeill" <jmcneill%netbsd.org@localhost>]

Module Name:    src
Committed By:   jmcneill
Date:           Fri Mar 23 09:43:33 UTC 2018

Modified Files:
        src/sys/arch/sgimips/mace: if_mec.c

Log Message:
No need to print interrupt status for RX underflow as this status bit is handled already


To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56 src/sys/arch/sgimips/mace/if_mec.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.