CVS commit: src/sys/dev/pci/ixgbe

["Kengo NAKAHARA" <knakahara%netbsd.org@localhost>]

Module Name:    src
Committed By:   knakahara
Date:           Fri Mar 30 03:56:38 UTC 2018

Modified Files:
        src/sys/dev/pci/ixgbe: ixgbe.c ixgbe.h

Log Message:
Fix the problem between eitr and link_speed.

In ixgbe_msix_que(), que->eitr_setting is limited to IXGBE_MIN_RSC_EITR_10G1G
when link_speed is 1Gbps or 10Gbps. However, que->eitr_setting is set to EITR
register in the *next* Tx/Rx interrupt. If link_speed changes from 100Mbps to
1Gbps ro 10Gbps, que->eitr_setting which is not limited can be set to EITR
register, that is, the problem fixed by ixgbe.c:r1.124 can occur in this case.

To fix this case, que->eitr_setting should be clear when link_speed is changed
or link state is changed.

Furthermore, expand the variants used for AIM (txr->bytes, txr->packets,
rxr->bytes and rxr->packets) from u32 to u64 to avoid wraparound which causes
que->eitr_setting calculation mistake.

XXX pullup-8


To generate a diff of this commit:
cvs rdiff -u -r1.137 -r1.138 src/sys/dev/pci/ixgbe/ixgbe.c
cvs rdiff -u -r1.37 -r1.38 src/sys/dev/pci/ixgbe/ixgbe.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.