CVS commit: src/sys/arch/mips/mips

["Izumi Tsutsui" <tsutsui%netbsd.org@localhost>]

Module Name:    src
Committed By:   tsutsui
Date:           Sun Jun 14 14:16:49 UTC 2020

Modified Files:
        src/sys/arch/mips/mips: cache.c

Log Message:
Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache.  PR/55138

Commented "I think this is bad copy&paste" from skrll@.
No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.


To generate a diff of this commit:
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/mips/mips/cache.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.