CVS commit: src/sys/arch

["Simon Burge" <simonb%netbsd.org@localhost>]

Module Name:    src
Committed By:   simonb
Date:           Mon Jun 15 07:48:12 UTC 2020

Modified Files:
        src/sys/arch/evbmips/cavium: machdep.c
        src/sys/arch/mips/cavium: octeonvar.h
        src/sys/arch/mips/cavium/dev: octeon_uart.c
        src/sys/arch/mips/conf: files.octeon
        src/sys/arch/mips/mips: mips_machdep.c
Added Files:
        src/sys/arch/mips/cavium: octeon_misc.c octeonreg.h

Log Message:
Finish CPU core support for Octeon Cavium CN70XX:
 - decode actual CPU name
 - per CPU core reset logic (partially adapted from OpenBSD)
 - handle Octeon 3 ioclock rate differences to other cores (from OpenBSD)


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/evbmips/cavium/machdep.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/cavium/octeon_misc.c \
    src/sys/arch/mips/cavium/octeonreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/cavium/octeonvar.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/cavium/dev/octeon_uart.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/conf/files.octeon
cvs rdiff -u -r1.291 -r1.292 src/sys/arch/mips/mips/mips_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.