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CVS commit: src/tests/lib/libc/gen
Module Name: src
Committed By: gson
Date: Mon Aug 24 06:55:16 UTC 2020
Modified Files:
src/tests/lib/libc/gen: t_siginfo.c
Log Message:
Expect a failure to trap unaligned acesses only when running under
qemu's TCG CPU emulation, not when running under hardware virtualization
such as qemu -accel nvmm.
To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/tests/lib/libc/gen/t_siginfo.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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