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CVS commit: src/sys/net



Module Name:    src
Committed By:   riastradh
Date:           Mon Aug 31 20:24:49 UTC 2020

Modified Files:
        src/sys/net: if_wg.c

Log Message:
wg: Fix byte order on wire.

Give this a chance to work on big-endian systems.


To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/net/if_wg.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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