CVS commit: src/sys/arch/mips/mips

["Simon Burge" <simonb%netbsd.org@localhost>]

Module Name:    src
Committed By:   simonb
Date:           Wed Sep  2 01:33:27 UTC 2020

Modified Files:
        src/sys/arch/mips/mips: mips_machdep.c

Log Message:
Octeon CN70XX CPUs have a COP0 config5 register.
XXX: The presense of these are defined by the MIPS architecture, should probe.


To generate a diff of this commit:
cvs rdiff -u -r1.299 -r1.300 src/sys/arch/mips/mips/mips_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.