CVS commit: src/sys/arch/arm/cortex

["Jared D. McNeill" <jmcneill%netbsd.org@localhost>]

Module Name:    src
Committed By:   jmcneill
Date:           Fri Dec  4 21:39:26 UTC 2020

Modified Files:
        src/sys/arch/arm/cortex: gicv3.c gicv3.h

Log Message:
gicv3: Only use 1 of N SPI distribution when the feature is available.

A GICv3+ implementation is not guaranteed to support 1 of N SPI
distribution. Support for this feature is indicated in GICD_TYPER.No1N.

When No1N=1, route all interrupts to the primary PE by default and only
allow a single CPU target when updating affinity.


To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gicv3.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.