CVS commit: src/sys/dev/ic

["matthew green" <mrg%netbsd.org@localhost>]

Module Name:    src
Committed By:   mrg
Date:           Sun Jan  9 00:36:28 UTC 2022

Modified Files:
        src/sys/dev/ic: dwc_eqos.c dwc_eqos_reg.h dwc_eqos_var.h

Log Message:
eqos: handle the GMAC_MTL_INTERRUPT_STATUS register having something

drain a couple of registers that want either a read or a write-1-to-
clear bit, and keep track of how many happen via evcnt.

i had this trigger one time, but not since adding instrumentation to
see exactly it was saying (the GMAC_MTL_INTERRUPT_STATUS_Q0IS bit was
set, and it requires some handling now implemented.)

ok jmcneill


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/dev/ic/dwc_eqos.c \
    src/sys/dev/ic/dwc_eqos_reg.h src/sys/dev/ic/dwc_eqos_var.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.