CVS commit: src/sys/arch/mips/cavium

["Taylor R Campbell" <riastradh%netbsd.org@localhost>]

Module Name:    src
Committed By:   riastradh
Date:           Sat Mar 26 19:38:00 UTC 2022

Modified Files:
        src/sys/arch/mips/cavium: octeon_intr.c

Log Message:
mips/cavium: Simplify membars around interrupt establishment.

Previously I used xc_barrier to ensure the initialization of the
struct octeon_intrhand was witnessed on all CPUs before publishing
it, in order to avoid needing any barrier on the usage side to be
issued by the interrupt handler.

But there's no need to avoid atomic_load_consume at time of
interrupt: on MIPS it's the same as atomic_load_relaxed anyway, so
there's no additional memory barrier cost here.


To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/mips/cavium/octeon_intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.