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CVS commit: src/sys/arch/powerpc/fpu
Module Name: src
Committed By: rin
Date: Wed Sep 14 05:54:07 UTC 2022
Modified Files:
src/sys/arch/powerpc/fpu: fpu_implode.c
Log Message:
Fix logic for FPSCR[UX]:
- Correct FPSCR[FPRF] field when round to 0.0 or 0.0f.
- Simplify.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/powerpc/fpu/fpu_implode.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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