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CVS commit: src/sys/arch/riscv/include
Module Name: src
Committed By: simonb
Date: Tue Nov 8 13:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: types.h
Log Message:
Add a #define for XLEN, the RISC-V native base integer ISA width.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/types.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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