CVS commit: src/sys/arch/riscv

["Simon Burge" <simonb%netbsd.org@localhost>]

Module Name:    src
Committed By:   simonb
Date:           Tue Nov 15 14:33:34 UTC 2022

Modified Files:
        src/sys/arch/riscv/include: sysreg.h
        src/sys/arch/riscv/riscv: pmap_machdep.c riscv_machdep.c vm_machdep.c

Log Message:
Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions.  Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/riscv/pmap_machdep.c
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/riscv/riscv_machdep.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/vm_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.