CVS commit: [netbsd-10] src/sys/arch/x86

["Martin Husemann" <martin%netbsd.org@localhost>]

Module Name:    src
Committed By:   martin
Date:           Tue Jul 25 11:41:42 UTC 2023

Modified Files:
        src/sys/arch/x86/include [netbsd-10]: cpu_extended_state.h
        src/sys/arch/x86/x86 [netbsd-10]: fpu.c

Log Message:
Pull up following revision(s) (requested by riastradh in ticket #244):

        sys/arch/x86/x86/fpu.c: revision 1.80
        sys/arch/x86/include/cpu_extended_state.h: revision 1.18

x86: Mitigate MXCSR Configuration Dependent Timing in kernel FPU use.

In fpu_kern_enter, make sure all the MXCSR exception status bits are
set when we start using the FPU, so that instructions which exhibit
MCDT are unaffected by it.

While here, zero all the other FPU registers in fpu_kern_enter.
In principle we could skip this step on future CPUs that fix the MCDT
bug, but there's probably not much benefit -- workloads that do a lot
of crypto in the kernel are probably better off using
kthread_fpu_enter or WQ_FPU to skip the fpu_kern_enter/leave cycles
in the first place.

For details, see:
https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/mxcsr-configuration-dependent-timing.html


To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.17.28.1 src/sys/arch/x86/include/cpu_extended_state.h
cvs rdiff -u -r1.79.4.1 -r1.79.4.2 src/sys/arch/x86/x86/fpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.