Re: standards on SIGFPE for divide by zero?

[mlelstv%serpens.de@localhost (Michael van Elst)]

riz%tastylime.net@localhost (Jeff Rizzo) writes:

>Someone else pointed me there, but perhaps I'm using it wrong... after doing
>fpsetmask(FP_X_DZ);
>The only thing different is that "1.0/0.0" prints "0" instead of "inf".  :/

Looks like no exception is generated. PowerPC has four exception modes:

none (set as default by the kernel)
imprecise non-recoverable (result is lost, exception happens later)
imprecise recoverable (result can be recovered, exception happens later)
precise (exception happens right after the operation, inhibits pipelining)

The default seems to be 'none' and I haven't found a place where
it is changed, but the trap handler allows userland to modify the
mode when it intercepts the privileged opcode.

The different enable bits controlled by fpsetmask() determine
wether the result of the operation is stored back, independent
from wether an exception is generated. So with fpsetmask() you
just get the old content of the floating point register (== 0)
and without you get the IEEE default result (== inf).

From "PowerPC User Instruction Set Architecture":
  Ignore Exceptions Mode should not, in general, be
  used when any FPSCR exception enable bits are
  set to 1.

Maybe fpsetmask() should just enable precise exception mode
even when it slows down FPU operations a lot.

-- 
-- 
                                Michael van Elst
Internet: mlelstv%serpens.de@localhost
                                "A potential Snark may lurk in every tree."