I noticed the June 4's source has been detecting Cyrix 486DLC and try to
set the internal cache into saftest state.  This is good for a non-DLC
specific board, but bad for a DLC-aware board because it's degrading 
performance.  Could the value of CCR0/CCR1 and cache region be set by
configuration file?  This will be more flexible.  Thanks.

-- 
   ________________________________________________________________________
  /             National Chiao Tung University in Taiwan                 / \
 |  Name: Yeng-Chee Su              Dept:  Computer Engineering         |__/
 |  Phone: +886-35-783513           E-mail: yenchee@csie.nctu.edu.tw    |
 |  Address: 22, Alley 2, Lane 173, Gao Tsui Road, HsinChu, Taiwan 300  |___ 
  \______________________________________________________________________\__/

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