On Mar 29,  1:30pm, jim@santafe.arch.columbia.edu (Jim Wise) wrote:
-- Subject: Re: Sparc/ELC's SLC's for sale

| At 4:40 PM 3/28/96, Christos Zoulas wrote:
| >I have 8-10 ELC's and 2 SLC's with 16Mb each that are just taking space
| >in our inventory room, and space in New York is expensive. They are all
| >in working order. I cannot just give them away, but I can take
| >reasonable offers (I consider around $500+shipping reasonable).
| 
| Tell me more about these machines?

These come with a built-in monochrome monitor. They are SS1+ class machines.
Something like a 486/33+...

Copyright (c) 1982, 1986, 1989, 1991, 1993
	The Regents of the University of California.  All rights reserved.

NetBSD 1.0A (SPARX) #3: Thu Mar  9 13:51:57 PST 1995
    root@sparx.deshaw.com:/tmp_mnt/src/local/NetBSD/NetBSD-current/src/sys/arch/sparc/compile/SPARX
real mem = 16......
avail mem = 15.....
using 507 buffers containing 2076672 bytes of memory
mainbus0 (root)
cpu0 at mainbus0: SUNW,Sun 4/25 (W8601/8701 or MB86903 @ 33 MHz, on-chip FPU)
cpu0: cache chip bug; trap page uncached
cpu0: 65536 byte write-through, 32 bytes/line, hw flush cache enabled
memreg0 at mainbus0 ioaddr 0xf4000000
clock0 at mainbus0 ioaddr 0xf2000000: mk48t02 (eeprom)
timer0 at mainbus0 ioaddr 0xf3000000
auxreg0 at mainbus0 ioaddr 0xf7400003
zs0 at mainbus0 ioaddr 0xf1000000 pri 12, softpri 6
zs1 at mainbus0 ioaddr 0xf0000000 pri 12, softpri 6
audio at mainbus0 ioaddr 0xf7201000 not configured
sbus0 at mainbus0 ioaddr 0xf8000000: clock = 20 MHz
dma0 at sbus0 slot 0 offset 0x400000: rev 1+
esp0 at sbus0 slot 0 offset 0x800000 pri 3: ESP100 20Mhz, target 7
scsibus0 at esp0
le0 at sbus0 slot 0 offset 0xc00000 pri 5: hardware address 08:00:20:03:a4:72
bwtwo0 at sbus0 slot 3 offset 0x0: SUNW,501-1561, 1152 x 900 (console)
fd at mainbus0 ioaddr 0xf7200000 not configured

christos