Subject: Re: Is gcc slow? Or is our gcc slow?
To: None <CURRENT-USERS@NetBSD.ORG>
From: None <formail.TCPBRIDGE.FS3.FAA1.STEVENG%smte@formail.formation.com>
List: current-users
Date: 04/10/1996 21:09:01
Hello All,
I'm not sure why you would want to re-run a failed bus cycle
but:
"4.2.4.2 RE-RUN OPERATION: When, during a bus cycle, the
processor receives a bus error signal and the halt pin is being
driver by an external device, the processor enters the re-run
sequence. ...
The processor terminates the bus cycle, then puts the address and
data output lines in the high-impedence state. The processor
remains "halted", and will not run another bus cycle until the
halt signal is removed by external logic. Then the processor
will re-run the previous cycle using the same function codes, the
same data (for a write operation), and the same controls. The
bus error signal should be removed at least one clock cycle
before the halt signal is removed."
The above is from a Motorola publication title "MC68000
16-/32-bit Microprocessor" and dated October, 1985. It is
labeled as advance info. Section 5.2.4.2 of the "M68000
8-/16-/32-Bit Microprocessor User's Manual", 8th ed, copyrighted
1990 has essentially the same info.
Happy hacking....
Steven Grunza
voice: (609) 234 - 5020 ext 3101
fax: (609) 234 - 5242
e-mail: steveng@formail.formation.com