I'm thinking of adding a new make variable modifier '=' (and '+=',
etc).  This message is to solicit feedback on the idea.

Motivation:

PR bin/10204 shows that the following does not work
due to the way that .for loops are implemented.

some/path/file.gz:
.for t in ${.TARGET} ${.TARGET:R}-blah.gz
	@echo t:T=${t:T}
	@echo t:R:T=${t:R:T}
.endfor

As the makefile is read, ${.TARGET} has no value, but t is expanded at
this point so ${t:T} comes out as nothing.  Using a variable
assignment modifier, the above .for loop could be read as.

some/path:
	${t:=${.TARGET}}
	@echo t:T=${t:T}
	@echo t:R:T=${t:R:T}
	${t:=${.TARGET}-blah}
	@echo t:T=${t:T}
	@echo t:R:T=${t:R:T}

and work as expected (I think ;-).  No expansion would be needed as
the makefile is parsed.  Obviously this is only of benefit to .for
loops appearing in target rules.  And one might need to do something
to ensure that lines with the assignments (which I believe should
expand to nothing) don't cause a problem.

In another case,  I have need of the += version within a .USE
target's rules.  It adds ${.TARGET} to a makefile.inc which
initializes a variable when read eg.

	echo FOO+=${.TARGET} >> foo.inc

and the rules test for ${FOO:M${.TARGET}} = '', obviously it would be
handy if the above snipet were.

	echo FOO+=${.TARGET} >> foo.inc; ${FOO:+=${.TARGET}}

so that the test would work correctly within the same make run.

Oh and doing =+ =? etc would be much simpler to parse than += ?=.

If anyone has any comments/suggestions I'd like to hear.

--sjg