On Sat, Jan 20, 2007 at 12:35:37PM -0500, Chris Ross wrote:
> 
> On Jan 20, 2007, at 12:12, Chris Ross wrote:
> >  The aforementioned "patch" I am now running with simply removes  
> >the PCI_PRODUCT_INTEL_82443BX_AGP & PCI_PRODUCT_INTEL_82443BX_AGP  
> >case starting near line 193 of pchbattach().  This is noted to be a  
> >"BIOS BUG WORKAROUND".  But, at least for my machine (pchb0: Intel  
> >82443BX Host Bridge/Controller (AGP disabled) (rev. 0x03)), this  
> >"workaround" causes the machine to get an NMI fairly easily.
> 
>   Ahh!  I think I figured this out.  According to a specification  
> update from Intel (available from http://www.intel.com/design/ 
> chipsets/specupdt/290639.htm ), it looks like this "issue" was  
> present in steppings A0, B0, and B1, but *not* C0 or C1.  (ref.  
> 'IPDTL Bit Setting' in table on PDF doc page #9)  So, "rev 0x03",  
> which my machine has, is stepping C1, and therefore the recommended  
> workaround should not apply.

What value does your bios set these bits to ?
From reading your mails (I've not looked at the Intel specs) it looks
as though the 2 bits modify the number of clocks in some part of the
DRAM memory cycle.
So I presume that changing them to 01 shortens the DRAM timings, which
probably causes memory errors when you populate all 4 memory slots
due to the additional capacitive load on the memory bus requiring
more relaxed timing.

	David

-- 
David Laight: david@l8s.co.uk