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Hi! all,


I think that i2c_bitbang is broken.  It changes the direction for the
check on status, and writes as it is.

I found following messages on OPENBLOCKS266.

  gpiic_read_bits: Read in output mode


The patch that sets the direction is appended. 

Thanks,
--
kiyohara

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Index: i2c_bitbang.c
===================================================================
RCS file: /cvsroot/src/sys/dev/i2c/i2c_bitbang.c,v
retrieving revision 1.7
diff -u -r1.7 i2c_bitbang.c
--- i2c_bitbang.c	30 Apr 2007 00:07:54 -0000	1.7
+++ i2c_bitbang.c	26 Nov 2007 03:04:07 -0000
@@ -64,6 +64,8 @@
 {
 	int bail = 0;
 
+	DIR(INPUT);
+
 	while (((READ & SCL) == 0) && (bail < SCL_BAIL_COUNT)) {
 
 		delay(1);
@@ -83,13 +85,15 @@
 {
 
 	DIR(OUTPUT);
-
 	SETBITS(SDA | SCL);
 	delay(5);		/* bus free time (4.7 uS) */
 	SETBITS(      SCL);
+
 	if (i2c_wait_for_scl(v, ops) != 0)
 		return EIO;
 	delay(4);		/* start hold time (4.0 uS) */
+
+	DIR(OUTPUT);
 	SETBITS(        0);
 	delay(5);		/* clock low time (4.7 uS) */
 
@@ -102,7 +106,6 @@
 {
 
 	DIR(OUTPUT);
-
 	SETBITS(      SCL);
 	delay(4);		/* stop setup time (4.0 uS) */
 	SETBITS(SDA | SCL);
@@ -157,29 +160,40 @@
 	uint8_t val = 0;
 	uint32_t bit;
 
-	DIR(INPUT);
+	DIR(OUTPUT);
 	SETBITS(SDA      );
 
 	for (i = 0; i < 8; i++) {
 		val <<= 1;
+
+		DIR(OUTPUT);
 		SETBITS(SDA | SCL);
+
 		if (i2c_wait_for_scl(v, ops) != 0)
 			return EIO;
 		delay(4);	/* clock high time (4.0 uS) */
+
+		DIR(INPUT);
 		if (READ & SDA)
 			val |= 1;
+
+		DIR(OUTPUT);
 		SETBITS(SDA      );
 		delay(5);	/* clock low time (4.7 uS) */
 	}
 
 	bit = (flags & I2C_F_LAST) ? SDA : 0;
+
 	DIR(OUTPUT);
 	SETBITS(bit      );
 	delay(1);	/* data setup time (250 nS) */
 	SETBITS(bit | SCL);
+
 	if (i2c_wait_for_scl(v, ops) != 0)
 		return EIO;
 	delay(4);	/* clock high time (4.0 uS) */
+
+	DIR(OUTPUT);
 	SETBITS(bit      );
 	delay(5);	/* clock low time (4.7 uS) */
 
@@ -202,29 +216,36 @@
 	uint8_t mask;
 	int error;
 
-	DIR(OUTPUT);
-
 	for (mask = 0x80; mask != 0; mask >>= 1) {
 		bit = (val & mask) ? SDA : 0;
+
+		DIR(OUTPUT);
 		SETBITS(bit      );
 		delay(1);	/* data setup time (250 nS) */
 		SETBITS(bit | SCL);
+
 		if (i2c_wait_for_scl(v, ops))
 			return EIO;
 		delay(4);	/* clock high time (4.0 uS) */
+
+		DIR(OUTPUT);
 		SETBITS(bit      );
 		delay(5);	/* clock low time (4.7 uS) */
 	}
 
-	DIR(INPUT);
-
+	DIR(OUTPUT);
 	SETBITS(SDA      );
 	delay(5);
 	SETBITS(SDA | SCL);
+
 	if (i2c_wait_for_scl(v, ops) != 0)
 		return EIO;
 	delay(4);
+
+	DIR(INPUT);
 	error = (READ & SDA) ? EIO : 0;
+
+	DIR(OUTPUT);
 	SETBITS(SDA      );
 	delay(5);
 

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