Re: AMD Phenom - need to enable L3 cache?

[Christoph Egger <Christoph_Egger%gmx.de@localhost>]

Paul Goyette wrote:
> I've just worked up a change to cpuctl to display L3 cache information
> (see PR bin/38679), and it appears that we don't have the L3 cache enabled:
>
> speedy {101} /build/obj/amd64/usr.sbin/cpuctl/cpuctl identify 0
> Cannot bind to target CPU.  Output may not accurately describe the target.
> Run as root to allow binding.
>
> cpu0: AMD Family 10h (686-class), 2310.80 MHz, id 0x100f22
> cpu0: features ffdbfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
> cpu0: features ffdbfbff<PGE,MCA,CMOV,PAT,PSE36,MPC,NOX,MMXX,MMX>
> cpu0: features ffdbfbff<FXSR,SSE,SSE2,RDTSCP,HTT,LONG,3DNOW2,3DNOW>
> cpu0: features2 802009<SSE3,MONITOR,CX16,POPCNT>
> cpu0: "AMD Phenom(tm) 9600 Quad-Core Processor"
> cpu0: I-cache 64kB 64B/line 2-way, D-cache 64kB 64B/line 2-way
> cpu0: L2 cache 512kB 64B/line 16-way
> cpu0: ITLB 32 4KB entries fully associative, 16 4MB entries fully 
> associative
> cpu0: DTLB 48 4KB entries fully associative, 48 4MB entries fully 
> associative
> cpu0: L3 cache 2048kB 64B/line disabled
> cpu0: Initial APIC ID 1
> cpu0: family 0f model 02 extfamily 01 extmodel 00
>
> Is there some explicit initialization needed to enable the L3 cache?

It is disabled by the BIOS on stepping 2 (TLB-Bug).
Stepping 3 has L3 cache enabled.

Christoph