Re: USB troubles with SB600/SB700 chipsets

[Markus W Kilbinger <mk%kilbi.de@localhost>]

>>>>> "Christoph" == Christoph Egger <Christoph_Egger%gmx.de@localhost> writes:

    Christoph> hm... maybe the quirk is applied too late. New attached
    Christoph> patch version applies it *before* the chip is enabled.

After applying this patch (#3) just leads to:

  ehci0 at pci0 dev 18 function 2: ATI Technologies SB700/SB800 USB EHCI 
Controller (rev. 0x00)
  ehci0: interrupting at ioapic0 pin 17
  ehci0: dropped intr workaround enabled
  ehci0: EHCI version 1.0
  ehci0: companion controllers, 3 ports each: ohci0 ohci1

, no amdehci (solution) so far. I'll provide some pcictl dump output
for these devs:

  $ pcictl /dev/pci0 list
  [...]
  000:18:0: ATI Technologies SB700/SB800 USB OHCI Controller (USB serial bus, 
interface 0x10)
  000:18:1: ATI Technologies SB700/SB800 USB OHCI Controller (USB serial bus, 
interface 0x10)
  000:18:2: ATI Technologies SB700/SB800 USB EHCI Controller (USB serial bus, 
interface 0x20)
  000:19:0: ATI Technologies SB700/SB800 USB OHCI Controller (USB serial bus, 
interface 0x10)
  000:19:1: ATI Technologies SB700/SB800 USB OHCI Controller (USB serial bus, 
interface 0x10)
  000:19:2: ATI Technologies SB700/SB800 USB EHCI Controller (USB serial bus, 
interface 0x20)
  000:20:0: ATI Technologies SB600/SB700/SB800 SMBus Controller (SMBus serial 
bus, revision 0x3a)

  pcictl /dev/pci0 dump -d 18       
  PCI configuration registers:
    Common header:
      0x00: 0x43971002 0x02a00117 0x0c031000 0x00804010
  
      Vendor Name: ATI Technologies (0x1002)
      Device Name: SB700/SB800 USB OHCI Controller (0x4397)
      Command register: 0x0117
        I/O space accesses: on
        Memory space accesses: on
        Bus mastering: on
        Special cycles: off
        MWI transactions: on
        Palette snooping: off
        Parity error checking: off
        Address/data stepping: off
        System error (SERR): on
        Fast back-to-back transactions: off
        Interrupt disable: off
      Status register: 0x02a0
        Capability List support: off
        66 MHz capable: on
        User Definable Features (UDF) support: off
        Fast back-to-back capable: on
        Data parity error detected: off
        DEVSEL timing: medium (0x1)
        Slave signaled Target Abort: off
        Master received Target Abort: off
        Master received Master Abort: off
        Asserted System Error (SERR): off
        Parity error detected: off
        DEVSEL timing: medium (0x1)
        Slave signaled Target Abort: off
        Master received Target Abort: off
        Master received Master Abort: off
        Asserted System Error (SERR): off
        Parity error detected: off
      Class Name: serial bus (0x0c)
      Subclass Name: USB (0x03)
      Interface: 0x10
      Revision ID: 0x00
      BIST: 0x00
      Header Type: 0x00+multifunction (0x80)
      Latency Timer: 0x40
      Cache Line Size: 0x10
  
    Type 0 ("normal" device) header:
      0x10: 0xfdffe000 0x00000000 0x00000000 0x00000000
      0x20: 0x00000000 0x00000000 0x00000000 0x834e1043
      0x30: 0x00000000 0x00000000 0x00000000 0x00000107
  
      Base address register at 0x10
        type: 32-bit nonprefetchable memory
        base: 0xfdffe000, not sized
      Base address register at 0x14
        not implemented(?)
      Base address register at 0x18
        not implemented(?)
      Base address register at 0x1c
        not implemented(?)
      Base address register at 0x20
        not implemented(?)
      Base address register at 0x24
        not implemented(?)
      Cardbus CIS Pointer: 0x00000000
      Subsystem vendor ID: 0x1043
      Subsystem ID: 0x834e
      Expansion ROM Base Address: 0x00000000
      Reserved @ 0x34: 0x00000000
      Reserved @ 0x38: 0x00000000
      Maximum Latency: 0x00
      Minimum Grant: 0x00
      Interrupt pin: 0x01 (pin A)
      Interrupt line: 0x07
  
    Device-dependent header:
      0x40: 0x00000380 0x00000011 0x00000000 0x00000000
      0x50: 0xf0011340 0x00000000 0xff543210 0x00000000
      0x60: 0x00000000 0x00000000 0x00000000 0x00000000
      0x70: 0x00000000 0x800000ff 0x00000000 0x00000000
      0x80: 0x00000000 0x00000000 0x00000000 0x00000000
      0x90: 0x000000000 0x00000000 0x00000000 0x00000000
      0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
      0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
      0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
      0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
      0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
      0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
  
  # pcictl /dev/pci0 dump -d 20 
  PCI configuration registers:
    Common header:
      0x00: 0x43851002 0x02300403 0x0c05003a 0x00800000
  
      Vendor Name: ATI Technologies (0x1002)
      Device Name: SB600/SB700/SB800 SMBus Controller (0x4385)
      Command register: 0x0403
        I/O space accesses: on
        Memory space accesses: on
        Bus mastering: off
        Special cycles: off
        MWI transactions: off
        Palette snooping: off
        Parity error checking: off
        Address/data stepping: off
        System error (SERR): off
        Fast back-to-back transactions: off
        Interrupt disable: on
      Status register: 0x0230
        Capability List support: on
        66 MHz capable: on
        User Definable Features (UDF) support: off
        Fast back-to-back capable: off
        Data parity error detected: off
        DEVSEL timing: medium (0x1)
        Slave signaled Target Abort: off
        Master received Target Abort: off
        Master received Master Abort: off
        Asserted System Error (SERR): off
        Parity error detected: off
      Class Name: serial bus (0x0c)
      Subclass Name: SMBus (0x05)
      Interface: 0x00
      Revision ID: 0x3a
      BIST: 0x00
      Header Type: 0x00+multifunction (0x80)
      Latency Timer: 0x00
      Cache Line Size: 0x00
  
    Type 0 ("normal" device) header:
      0x10: 0x00000000 0x00000000 0x00000000 0x00000000
      0x20: 0x00000000 0x00000000 0x00000000 0x834e1043
      0x30: 0x00000000 0x000000b0 0x00000000 0x00000000
  
      Base address register at 0x10
        not implemented(?)
      Base address register at 0x14
        not implemented(?)
      Base address register at 0x18
        not implemented(?)
      Base address register at 0x1c
        not implemented(?)
      Base address register at 0x20
        not implemented(?)
      Base address register at 0x24
        not implemented(?)
      Cardbus CIS Pointer: 0x00000000
      Subsystem vendor ID: 0x1043
      Subsystem ID: 0x834e
      Expansion ROM Base Address: 0x00000000
      Capability list pointer: 0xb0
      Reserved @ 0x38: 0x00000000
      Maximum Latency: 0x00
      Minimum Grant: 0x00
      Interrupt pin: 0x00 (none)
      Interrupt line: 0x00
  
    Capability register at 0xb0
      type: 0x08 (LDT)
  
    Device-dependent header:
      0x40: 0xfc006b44 0x00000000 0x0000ff0f 0x80000000
      0x50: 0x08f001f0 0x0ff008f4 0x0ff00b21 0x00000000
      0x60: 0xa8240001 0x0fdefcbf 0x000090ff 0x00000020
      0x70: 0x00000000 0xfec00008 0x00006eff 0x0ff00000
      0x80: 0x0ff00af0 0x00000000 0x00000000 0x00000000
      0x90: 0x00000b01 0x00ffdeeb 0x00000000 0x00000000
      0xa0: 0xffff0000 0x09f0ff7f 0x0508ff10 0x18207106
      0xb0: 0xa8020008 0xfed00000 0x00000000 0x1a080ff0
      0xc0: 0xffffffff 0x00000000 0x00000000 0x00000000
      0xd0: 0x00010000 0x00000000 0x00000000 0x00000000
      0xe0: 0x0000b920 0x00000000 0x00000000 0x00000000
      0xf0: 0x00000cd8 0x00440000 0x00000000 0x00120082

Regards, Markus.