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NEXCOM VTC100
Hi!
NEXCOM VTC100 is supported under arch/evbarm/beagle with some patches.
VTC100 works by TI Sittara AM3359. The configuration file VTC100 was
copy and edit from BEAGLEBONE.
http://www.nexcom.com/Products/mobile-computing-solutions/in-vehicle-pc/in-vehicle-pc/car-pc-vtc-100
But USB and Ethernet not support yet.
Also edma and tiotg attaches at mainbus. And obio0 split to obio[012],
like BEAGLEBOARD.
And our PMIC is TPS65910, not TPS65217.
Thanks,
--
kiyohara
U-Boot SPL 2011.09 (Jun 30 2016 - 07:22:14)
Texas Instruments Revision detection unimplemented
OMAP SD/MMC: 0
reading u-boot.img
reading u-boot.img
U-Boot 2011.09 (Jun 27 2016 - 09:24:32)
I2C: ready
DRAM: 256 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - readenv() failed, using default environment
Hit any key to stop autoboot: 0
U-Boot# mmc rescan
U-Boot# fatload mmc 0 82000000 nnetbsd.gz.ub
reading nnetbsd.gz.ub
1689163 bytes read
U-Boot# bootm 82000000
## Booting kernel from Legacy Image at 82000000 ...
Image Name: NetBSD/beagle 7.99.31
Image Type: ARM NetBSD Kernel Image (gzip compressed)
Data Size: 1689099 Bytes = 1.6 MiB
Load Address: 80300000
Entry Point: 80300000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
## Transferring control to NetBSD stage-2 loader (at address 80300000) ...
uboot arg = 0x8ff7cfe8, 0, 0x8ffb43c9, 0x8ffb43c9
[ Kernel symbol table missing! ]
Loaded initial symtab at 0x8062e2b0, strtab at 0x8065f300, # entries 12530
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 7.99.31 (VTC100) #0: Thu Jun 30 17:27:25 JST 2016
ax%www23011ue.sakura.ne.jp@localhost:/home/ax/NetBSD/test/src/sys/arch/evbarm/compile/VTC100
total memory = 256 MB
avail memory = 246 MB
sysctl_createv: sysctl_create(machine_arch) returned 17
timecounter: Timecounters tick every 10.000 msec
mainbus0 (root)
cpu0 at mainbus0 core 0: 720 MHz Cortex-A8 r3p2 (Cortex V7A core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB/64B 4-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache
vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
obio0 at mainbus0 base 0x44c00000-0x44ffffff: On-Board IO
prcm0 at obio0 addr 0x44e00000-0x44e01fff: Power, Reset and Clock Management
sitaracm0 at obio0 addr 0x44e10000-0x44e11fff: control module, rev 1.0
obio1 at mainbus0 base 0x48000000-0x48ffffff: On-Board IO
omapgpio1 at obio1 addr 0x4804c000-0x4804cfff
gpio1 at omapgpio1: 32 pins
omapgpio2 at obio1 addr 0x481ac000-0x481acfff
gpio2 at omapgpio2: 32 pins
omapgpio3 at obio1 addr 0x481ae000-0x481aefff
gpio3 at omapgpio3: 32 pins
omapicu0 at obio1 addr 0x48200000-0x48200fff intrbase 0
obio2 at mainbus0 base 0x4a000000-0x4affffff: On-Board IO
gpmc0 at mainbus0 base 0x50000000: General Purpose Memory Controller, rev 6.0
gpmc0: CS#0 valid, addr 0x08000000, size 256MB
edma0 at mainbus0 base 0x49000000-0x490fffff
tiotg0 at mainbus0 base 0x47400000-0x47404fff: TI dual-port USB controller: version v1.0.0.13
motg0 at tiotg0 port 0: 0x4ea20800 version v0.0.0
motg1 at tiotg0 port 1: 0x4ea20800 version v0.0.0
motg1: Dynamic FIFO sizing detected, assuming 16Kbytes of FIFO RAM
usb0 at motg1: USB revision 2.0
omapgpio0 at obio0 addr 0x44e07000-0x44e07fff
gpio0 at omapgpio0: 32 pins
tiiic0 at obio0 addr 0x44e0b000-0x44e0bfff intr 70: rev 0.11
iic0 at tiiic0: I2C bus
tps65910pm0 at iic0 addr 0x12: SmartReflex
tps65910pm1 at iic0 addr 0x2d: RTC, Thermal
omapdmtimer1 at obio0 addr 0x44e31000-0x44e31fff intr 67: DMTIMER1ms
omapwdt32k0 at obio0 addr 0x44e35000-0x44e35fff: rev 0.1
com0 at obio1 addr 0x48022000-0x48022fff intr 73: ns16550a, working fifo
com0: console
com1 at obio1 addr 0x481a6000-0x481a6fff intr 44: ns16550a, working fifo
sdhc0 at obio1 addr 0x48060000-0x48060fff intr 64sdhc0: EDMA tx channel 24, rx channel 25
: SDHC controller (EDMA)
sdhc0: SDHC 2.0, rev 49, platform DMA, 96000 kHz, HS 1.8V 3.0V, 1024 byte blocks
sdmmc0 at sdhc0 slot 0
omapdmtimer0 at obio1 addr 0x48040000-0x48040fff intr 68: DMTIMER2
omapdmtimer2 at obio1 addr 0x48044000-0x48044fff intr 92: DMTIMER4
cpsw0 at obio2 addr 0x4a100000-0x4a107fff intrbase 93: TI CPSW Ethernet
cpsw0: Ethernet address c4:ed:ba:89:85:7d
ukphy0 at cpsw0 phy 0: OUI 0x00c82e, model 0x0007, rev. 4
ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseSX-FDX, 1000baseT-FDX, auto
cpsw0: 1000baseT PHY found. Setting RGMII Mode
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
timecounter: Timecounter "dmtimer" frequency 24000000 Hz quality 100
uhub0 at usb0: Mentor Graphics MOTG root hub, class 9/0, rev 2.00/1.00, addr 1
uhub0: 1 port with 1 removable, self powered
ld0 at sdmmc0: <0x03:0x5344:SL32G:0x80:0x0ff1051e:0x0ec>
ld0: 30436 MB, 7729 cyl, 128 head, 63 sec, 512 bytes/sect x 62333952 sectors
ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
boot device: <unknown>
root device: ld0
dump device (default ld0b):
file system (default generic):
root on ld0a dumps on ld0b
mountroot: trying ext2fs...
mountroot: trying ffs...
root file system type: ffs
kern.module.path=/stand/evbarm/7.99.31/modules
WARNING: clock gained 4 days
init path (default /sbin/init):
init: copying out path `/sbin/init' 11
/etc/rc.conf is not configured. Multiuser boot aborted.
Enter pathname of shell or RETURN for /bin/sh:
We recommend that you create a non-root account and use su(1) for root access.
#
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