>Number:         3559
>Category:       kern
>Synopsis:       diffs to add ESP406 and FAS408 to ncr53c9x MI code
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    kern-bug-people (Kernel Bug People)
>State:          open
>Class:          change-request
>Submitter-Id:   net
>Arrival-Date:   Tue Apr 29 22:35:02 1997
>Last-Modified:
>Originator:     Eric S. Hvozda
>Organization:
	
>Release:        1.2
>Environment:
	
System: NetBSD bell 1.2 NetBSD 1.2 (BELL) #0: Tue Feb 4 00:55:10 EST 1997 hvozda@bell:/usr/src/sys/arch/i386/compile/BELL i386


>Description:
	No support for ESP406 or FAS408 in ncr53c9x MI code
>How-To-Repeat:
	Attempt to create a isa or pcmcia based driver for either the
	ESP406 and FAS408 and discover that the ncr53c9x MI code
	needs just a few more tweeks.
>Fix:
	Apply the paches below, they add support for both the
	ESP406 and FAS408.  These aic's are used in Qlogic's
	pcmcia, isa, and vlb offerings.  These patches are for a 
	soon to be submitted isa based esp driver.

*** ncr53c9xvar.h.esh	Mon Apr 28 12:30:30 1997
--- ncr53c9xvar.h	Tue Apr 29 11:16:00 1997
***************
*** 77,83 ****
  #define	NCR_VARIANT_ESP200		2
  #define	NCR_VARIANT_NCR53C94		3
  #define	NCR_VARIANT_NCR53C96		4
! #define	NCR_VARIANT_MAX			5
  
  /*
   * ECB. Holds additional information for each SCSI command Comments: We
--- 77,85 ----
  #define	NCR_VARIANT_ESP200		2
  #define	NCR_VARIANT_NCR53C94		3
  #define	NCR_VARIANT_NCR53C96		4
! #define	NCR_VARIANT_ESP406		5
! #define	NCR_VARIANT_FAS408		6
! #define	NCR_VARIANT_MAX			7
  
  /*
   * ECB. Holds additional information for each SCSI command Comments: We
*** ncr53c9x.c.esh	Sun Apr 27 22:36:53 1997
--- ncr53c9x.c	Tue Apr 29 20:55:04 1997
***************
*** 131,136 ****
--- 131,138 ----
  	"ESP200",
  	"NCR53C94",
  	"NCR53C96",
+ 	"ESP406",
+ 	"FAS408",
  };
  
  /*
***************
*** 197,202 ****
--- 199,215 ----
  	 * Now try to attach all the sub-devices
  	 */
  	config_found(&sc->sc_dev, &sc->sc_link, scsiprint);
+ 
+ 	/*
+ 	 * Enable interupts from the SCSI core
+ 	 */
+ 	if ((sc->sc_rev == NCR_VARIANT_ESP406) ||
+ 	    (sc->sc_rev == NCR_VARIANT_FAS408)) {
+ 		NCR_PIOREGS(sc);
+ 		NCR_WRITE_REG(sc, NCR_CFG5, NCRCFG5_SINT |
+ 		    NCR_READ_REG(sc, NCR_CFG5));
+ 		NCR_SCSIREGS(sc);
+ 	}
  }
  
  /*
***************
*** 222,227 ****
--- 235,243 ----
  
  	/* do these backwards, and fall through */
  	switch (sc->sc_rev) {
+ 	case NCR_VARIANT_ESP406:
+ 	case NCR_VARIANT_FAS408:
+ 		NCR_SCSIREGS(sc);
  	case NCR_VARIANT_NCR53C94:
  	case NCR_VARIANT_NCR53C96:
  	case NCR_VARIANT_ESP200:
***************
*** 1244,1250 ****
  	size_t size;
  	int nfifo;
  
! 	NCR_TRACE(("[ncr53c9x_intr]"));
  
  	/*
  	 * I have made some (maybe seriously flawed) assumptions here,
--- 1260,1266 ----
  	size_t size;
  	int nfifo;
  
! 	NCR_TRACE(("[ncr53c9x_intr] "));
  
  	/*
  	 * I have made some (maybe seriously flawed) assumptions here,
*** ncr53c9xreg.h.esh	Sun Mar 16 07:28:11 1997
--- ncr53c9xreg.h	Tue Apr 29 20:38:11 1997
***************
*** 147,149 ****
--- 147,176 ----
  #define  NCRCFG3_CDB	0x04		/*	CDB 10-bytes OK		*/
  #define  NCRCFG3_FSCSI	0x02		/*	Fast SCSI		*/
  #define  NCRCFG3_FCLK	0x01		/*	Fast Clock (>25Mhz)	*/
+ 
+ /* Config #4 only on ESP406 or FAS408 */
+ #define	NCR_CFG4	0x0d		/* RW - Configuration #4	*/
+ #define	 NCRCFG4_CRS1	0x80		/*	Select register set #1	*/
+ #define	 NCRCFG4_RSVD1	0x40		/*	reserved		*/
+ #define	 NCRCFG4_RSVD2	0x20		/*	reserved		*/
+ #define	 NCRCFG4_RSVD3	0x10		/*	reserved		*/
+ #define	 NCRCFG4_RSVD4	0x08		/*	reserved		*/
+ #define	 NCRCFG4_ACTNEG	0x04		/*	Active negation		*/
+ #define	 NCRCFG4_RSVD5	0x02		/*	reserved		*/
+ #define	 NCRCFG4_RSVD6	0x01		/*	reserved		*/
+ 
+ #define	NCR_SCSIREGS(sc) do { NCR_WRITE_REG(sc, NCR_CFG4, \
+ 	~NCRCFG4_CRS1 & NCR_READ_REG(sc, NCR_CFG4)); } while(0)
+ #define	NCR_PIOREGS(sc) do { NCR_WRITE_REG(sc, NCR_CFG4, \
+ 	NCRCFG4_CRS1 | NCR_READ_REG(sc, NCR_CFG4)); } while(0)
+ 
+ /* Config #5 only on ESP406 or FAS408 */
+ #define	NCR_CFG5	0x0d		/* RW - Configuration #5	*/
+ #define	 NCRCFG5_CRS1	0x80		/*	Select register set #1	*/
+ #define	 NCRCFG5_SRAM	0x40		/*	SRAM memory map		*/
+ #define  NCRCFG5_AADDR	0x20		/*	Auto address		*/
+ #define  NCRCFG5_PTRINC	0x10		/*	Pointer increment	*/
+ #define  NCRCFG5_LOWPWR	0x08		/*	Low power mode		*/
+ #define  NCRCFG5_SINT	0x04		/*	SCSI interupt enable	*/
+ #define  NCRCFG5_INTP	0x02		/*	INT polarity		*/
+ #define  NCRCFG5_AINT	0x01		/*	ATA interupt enable	*/
>Audit-Trail:
>Unformatted: