>Number:         4340
>Category:       port-x68k
>Synopsis:       The mha driver does not work except X68030 w/ 680[46]0
>Confidential:   no
>Severity:       serious
>Priority:       high
>Responsible:    gnats-admin (GNATS administrator)
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Fri Oct 24 14:35:01 1997
>Last-Modified:
>Originator:     Takeshi Nakayama
>Organization:
Tokai Communication Platform for Inter Person
>Release:        NetBSD-current [Oct 23 1997]
>Environment:
  X68000XVI w/ Xellent30, MK-HA1 Mach2 SCSI host adaptor
System:
  NetBSD selene NetBSD 1.3_ALPHA (SELENE) #7: Sat Oct 25 05:02:01 JST 1997
  takeshi@lethe:/var/src/sys/arch/x68k/compile/SELENE x68k

>Description:
The mha driver has two probrems as follows:

1. It uses DCFP() cache flush function for MC680[46]0 without a MMU
type checking code.

2. Always uses the X68030 short bus cycle mode.

>How-To-Repeat:
1. A kernel compile fails only `options M68030' specified.

2. Run on the machine except X68030 w/ 680[46]0.

>Fix:
The following patch corrects these probrems probably....

*** src/sys/arch/x68k/dev/mha.c	Mon Oct 20 23:23:38 1997
--- obj/sys/arch/x68k/dev/mha.c	Sat Oct 25 04:51:12 1997
***************
*** 49,54 ****
--- 49,66 ----
  #define SPC_USE_SYNCHRONOUS	0
  #define SPC_SYNC_REQ_ACK_OFS 	8
  
+ /* Default DMA mode? */
+ #define MHA_DMA_LIMIT_XFER	1
+ #define MHA_DMA_BURST_XFER	1
+ #define MHA_DMA_SHORT_BUS_CYCLE	1
+ 
+ #define MHA_DMA_DATAIN	(0 | (MHA_DMA_LIMIT_XFER << 1)		\
+ 			   | (MHA_DMA_BURST_XFER << 2)		\
+ 			   | (MHA_DMA_SHORT_BUS_CYCLE << 3))
+ #define MHA_DMA_DATAOUT	(1 | (MHA_DMA_LIMIT_XFER << 1)		\
+ 			   | (MHA_DMA_BURST_XFER << 2)		\
+ 			   | (MHA_DMA_SHORT_BUS_CYCLE << 3))
+ 
  /* Include debug functions?  At the end of this file there are a bunch of
   * functions that will print out various information regarding queued SCSI
   * commands, driver state and chip contents.  You can call them from the
***************
*** 1607,1617 ****
  
    vaddr = p;
    paddr = (char *)kvtop(vaddr);
!   DCFP((vm_offset_t)paddr);	/* XXX */
    for (ts = (NBPG - ((long)vaddr & PGOFSET));
         ts < n && (char *)kvtop(vaddr + ts + 4) == paddr + ts + 4;
         ts += NBPG)
!     DCFP((vm_offset_t)paddr + ts);
    if (ts > n)
      ts = n;
  #if 0
--- 1619,1645 ----
  
    vaddr = p;
    paddr = (char *)kvtop(vaddr);
! #if MHA_DMA_SHORT_BUS_CYCLE == 1
!   if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((vm_offset_t)paddr >> 19)))
!     dw &= ~(1 << 3);
! #endif
! #if defined(M68040) || defined(M68060)
! #if defined(M68020) || defined(M68030)
!   if (mmutype == MMU_68040)
! #endif
!     DCFP((vm_offset_t)paddr);	/* XXX */
! #endif
    for (ts = (NBPG - ((long)vaddr & PGOFSET));
         ts < n && (char *)kvtop(vaddr + ts + 4) == paddr + ts + 4;
         ts += NBPG)
! #if defined(M68040) || defined(M68060)
! #if defined(M68020) || defined(M68030)
!     if (mmutype == MMU_68040)
! #endif
!       DCFP((vm_offset_t)paddr + ts);
! #else
!     ;
! #endif
    if (ts > n)
      ts = n;
  #if 0
***************
*** 1648,1654 ****
  
    if (((long)p & 1) || (n & 1))
      return mha_dataout_pio(sc, p, n);
!   return mha_dataio_dma(0x000F, CMD_SEND_FROM_DMA, sc, p, n);
  }
  
  int
--- 1676,1682 ----
  
    if (((long)p & 1) || (n & 1))
      return mha_dataout_pio(sc, p, n);
!   return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n);
  }
  
  int
***************
*** 1665,1671 ****
      return n;
    if (acb->cmd.opcode == 0x03 || ((long)p & 1) || (n & 1))
      return mha_datain_pio(sc, p, n);
!   return mha_dataio_dma(0x000E, CMD_RECEIVE_TO_DMA, sc, p, n);
  }
  
  
--- 1693,1699 ----
      return n;
    if (acb->cmd.opcode == 0x03 || ((long)p & 1) || (n & 1))
      return mha_datain_pio(sc, p, n);
!   return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n);
  }
  
  
>Audit-Trail:
>Unformatted: