>Number:         18641
>Category:       kern
>Synopsis:       PCMCIA 3.3V support patch for Ricoh PCIC
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    kern-bug-people
>State:          open
>Class:          change-request
>Submitter-Id:   net
>Arrival-Date:   Sun Oct 13 03:30:00 PDT 2002
>Closed-Date:
>Last-Modified:
>Originator:     Hiroshi Noguchi
>Release:        1.6
>Organization:
none
>Environment:
NetBSD mg2 1.6I NetBSD 1.6I (MCR530) #0: Sun Oct  6 01:10:06 JST 2002     noguchi@mg2:/mnt/CURRENT/sys.MG2/arch/hpcmips/compile/MCR530 hpcmips

>Description:
This patch supports PCMCIA's 3.3V for Ricoh RF5C296/RF5C396 (non-CardBus PCIC)


--- sys.org/dev/ic/i82365.c	Mon Jun 24 07:05:00 2002
+++ sys.MG2/dev/ic/i82365.c	Fri Sep 27 16:32:32 2002
@@ -119,6 +119,7 @@
 	struct pcic_handle *h;
 {
 	int reg;
+	int	vendor;
 
 	/*
 	 * the chip_id of the cirrus toggles between 11 and 00 after a write.
@@ -141,12 +142,46 @@
 
 	reg = pcic_read(h, PCIC_IDENT);
 
-	if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0)
-		return (PCIC_VENDOR_I82365SLR0);
-	else
-		return (PCIC_VENDOR_I82365SLR1);
+	switch( reg ){
+	  case PCIC_IDENT_ID_INTEL0:
+		vendor = PCIC_VENDOR_I82365SLR0;
+		goto l_check_ricoh;
+
+	  case PCIC_IDENT_ID_INTEL1:
+		vendor = PCIC_VENDOR_I82365SLR1;
+
+	  l_check_ricoh:;
+		/*
+		 * check for Ricoh RF5C[23]96
+		 */
+		reg = pcic_read( h, PCIC_RICOH_REG_CHIP_ID );
+		switch( reg ){
+		  case PCIC_RICOH_CHIP_ID_5C296:
+			vendor = PCIC_VENDOR_RICOH_5C296;
+			break;
+		  case PCIC_RICOH_CHIP_ID_5C396:
+			vendor = PCIC_VENDOR_RICOH_5C396;
+			break;
+		  default:
+			break;
+		}
+		break;
+	  case PCIC_IDENT_ID_INTEL2:
+		vendor = PCIC_VENDOR_I82365SL_DF;
+		break;
+	  case PCIC_IDENT_ID_IBM1:
+	  case PCIC_IDENT_ID_IBM2:
+		vendor = PCIC_VENDOR_IBM;
+		break;
+	  case PCIC_IDENT_ID_IBM3:
+		vendor = PCIC_VENDOR_IBM_KING;
+		break;
+	  default:
+		vendor = PCIC_VENDOR_UNKNOWN;
+		break;
+	}
 
-	return (PCIC_VENDOR_UNKNOWN);
+	return ( vendor );
 }
 
 char *
@@ -162,6 +197,16 @@
 		return ("Cirrus PD6710");
 	case PCIC_VENDOR_CIRRUS_PD672X:
 		return ("Cirrus PD672X");
+	case PCIC_VENDOR_I82365SL_DF:
+		return ("Intel 82365SL-DF");
+	case PCIC_VENDOR_RICOH_5C296:
+		return ("Ricoh RF5C296");
+	case PCIC_VENDOR_RICOH_5C396:
+		return ("Ricoh RF5C396");
+	case PCIC_VENDOR_IBM:
+		return ("IBM PCIC");
+	case PCIC_VENDOR_IBM_KING:
+		return ("IBM KING");
 	}
 
 	return ("Unknown controller");
@@ -1386,6 +1431,37 @@
 	 * we are changing Vcc (Toff).
 	 */
 	pcic_delay(h, 300 + 100, "pccen0");
+
+	/*
+	 * power hack for RICOH RF5C[23]96
+	 */
+	switch( h->vendor ){
+	  case PCIC_VENDOR_RICOH_5C296:
+	  case PCIC_VENDOR_RICOH_5C396:
+		do{
+			int	vcc_3v = 0;
+			int	regtmp;
+
+			if( (pcic_read( h, PCIC_CARD_DETECT ) & PCIC_CARD_DETECT_GPI_ENABLE) == 0 ){
+				vcc_3v = (pcic_read( h, PCIC_IF_STATUS ) & PCIC_IF_STATUS_GPI) ? 1 : 0;
+				DPRINTF( ("\nGPI pin = %s\n", vcc_3v ? "1 (3.3V ready?)" : "0 (5V only?)") );
+			} else{
+				DPRINTF( ("\nGPI Enable pin is enabled. Can't use to sense VS1\n") );
+			}
+
+			regtmp = pcic_read( h, PCIC_RICOH_REG_MCR2 );
+			regtmp &= ~PCIC_RICOH_MCR2_VCC_SEL_MASK;
+			if( vcc_3v ){
+				regtmp |= PCIC_RICOH_MCR2_VCC_SEL_3V;
+			} else{
+				regtmp |= PCIC_RICOH_MCR2_VCC_SEL_5V;
+			}
+			pcic_write( h, PCIC_RICOH_REG_MCR2, regtmp );
+		} while( 0 );
+		break;
+	  default:
+		break;
+	}
 
 #ifdef VADEM_POWER_HACK
 	bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e);
--- sys.org/dev/ic/i82365reg.h	Mon Jun 24 07:05:00 2002
+++ sys.MG2/dev/ic/i82365reg.h	Fri Sep 27 16:38:19 2002
@@ -63,6 +63,13 @@
 #define	PCIC_IDENT_REV_I82365SLR0		0x02
 #define	PCIC_IDENT_REV_I82365SLR1		0x03
 
+#define	PCIC_IDENT_ID_INTEL0		0x82
+#define	PCIC_IDENT_ID_INTEL1		0x83
+#define	PCIC_IDENT_ID_INTEL2		0x84
+#define	PCIC_IDENT_ID_IBM1			0x88
+#define	PCIC_IDENT_ID_IBM2			0x89
+#define	PCIC_IDENT_ID_IBM3			0x8A
+
 #define	PCIC_IF_STATUS				0x01	/* RO */
 #define	PCIC_IF_STATUS_GPI			0x80 /* General Purpose Input */
 #define	PCIC_IF_STATUS_POWERACTIVE		0x40
@@ -336,3 +343,11 @@
 #define PCIC_CIRRUS_EXTENDED_DATA		0x2F
 #define PCIC_CIRRUS_EXT_CONTROL_1		0x03
 #define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK	0x18
+
+#define	PCIC_RICOH_REG_CHIP_ID			0x3A
+#define	PCIC_RICOH_CHIP_ID_5C296			0x32
+#define	PCIC_RICOH_CHIP_ID_5C396			0xB2
+#define	PCIC_RICOH_REG_MCR2				0x2F
+#define	PCIC_RICOH_MCR2_VCC_SEL_MASK		0x01
+#define	PCIC_RICOH_MCR2_VCC_SEL_3V			0x01
+#define	PCIC_RICOH_MCR2_VCC_SEL_5V			0x00
--- sys.org/dev/ic/i82365var.h	Mon Jun 24 07:05:00 2002
+++ sys.MG2/dev/ic/i82365var.h	Fri Sep 27 16:39:01 2002
@@ -100,6 +100,11 @@
 #define	PCIC_VENDOR_I82365SLR1		2
 #define	PCIC_VENDOR_CIRRUS_PD6710	3
 #define	PCIC_VENDOR_CIRRUS_PD672X	4
+#define	PCIC_VENDOR_I82365SL_DF		5
+#define	PCIC_VENDOR_IBM				6
+#define	PCIC_VENDOR_IBM_KING		7
+#define	PCIC_VENDOR_RICOH_5C296		8
+#define	PCIC_VENDOR_RICOH_5C396		9
 
 /*
  * This is sort of arbitrary.  It merely needs to be "enough". It can be

>How-To-Repeat:

>Fix:

>Release-Note:
>Audit-Trail:
>Unformatted: