>Number:         21108
>Category:       kern
>Synopsis:       if_wi_pci.c rev 1.21 is incorrect for PLX-9052
>Confidential:   no
>Severity:       serious
>Priority:       high
>Responsible:    kern-bug-people
>State:          open
>Class:          change-request
>Submitter-Id:   net
>Arrival-Date:   Sat Apr 12 01:12:00 PDT 2003
>Closed-Date:
>Last-Modified:
>Originator:     Christopher SEKIYA
>Release:        NetBSD 1.6R
>Organization:

-- Chris
	GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5  938E 023E EEFB FEB9 DE7F)
>Environment:
	
	
System: NetBSD izu 1.6R NetBSD 1.6R (IZU) #5: Sat Apr 12 11:21:59 JST 2003 root@izu:/usr/builder/sys/arch/i386/compile/IZU i386
Architecture: i386
Machine: i386
>Description:
	Revision 1.21 of if_wi_pci.c, which aimed to properly support wi cards
	behind PLX bridges, assumed that all PLX bridges had i/o at 0x14.

	This is incorrect for the PLX-9052 as used in Corega cards, at least.
	1.21 actually broke previously working Corega support.
>How-To-Repeat:
	Attempt to use -current with a Corega PCCL-11.  Watch it fail to 
	map the PLX.
>Fix:
	This diff adds a conditional for the PLX-9052.  if_wi_pci.c will now
	not try to map/utilize the PLX i/o space if the card specifies that it
	has a 9052.  My card works perfectly with this patch.

Index: if_wi_pci.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_wi_pci.c,v
retrieving revision 1.22
diff -u -r1.22 if_wi_pci.c
--- if_wi_pci.c	2003/03/29 20:49:04	1.22
+++ if_wi_pci.c	2003/04/12 02:26:38
@@ -75,6 +75,9 @@
 #define WI_PCI_LOMEM		0x18	/* ISA membase */
 #define WI_PCI_LOIO		0x1C	/* ISA iobase */
 
+#define CHIP_PLX_OTHER		0x01
+#define CHIP_PLX_9052		0x02
+
 #define WI_PLX_COR_OFFSET       0x3E0
 #define WI_PLX_COR_VALUE        0x41
 
@@ -108,21 +111,21 @@
 	int			wpp_plx;	/* uses PLX chip */
 } wi_pci_products[] = {
 	{ PCI_VENDOR_GLOBALSUN,		PCI_PRODUCT_GLOBALSUN_GL24110P,
-	  NULL, 1 },
+	  NULL, CHIP_PLX_OTHER },
 	{ PCI_VENDOR_GLOBALSUN,		PCI_PRODUCT_GLOBALSUN_GL24110P02,
-	  NULL, 1 },
+	  NULL, CHIP_PLX_OTHER },
 	{ PCI_VENDOR_EUMITCOM,		PCI_PRODUCT_EUMITCOM_WL11000P,
-	  NULL, 1 },
+	  NULL, CHIP_PLX_OTHER },
 	{ PCI_VENDOR_3COM,		PCI_PRODUCT_3COM_3CRWE777A,
-	  NULL, 1 },
+	  NULL, CHIP_PLX_OTHER },
 	{ PCI_VENDOR_NETGEAR,		PCI_PRODUCT_NETGEAR_MA301,
-	  NULL, 1 },
+	  NULL, CHIP_PLX_OTHER },
 	{ PCI_VENDOR_INTERSIL,		PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN,
 	  "Intersil Prism2.5", 0 },
 	{ PCI_VENDOR_NDC,		PCI_PRODUCT_NDC_NCP130,
-	  NULL, 1 },
+	  NULL, CHIP_PLX_9052 },
 	{ PCI_VENDOR_USR2,		PCI_PRODUCT_USR2_2415,
-	  NULL, 1 },
+	  NULL, CHIP_PLX_OTHER },
 	{ 0,				0,
 	  NULL, 0},
 };
@@ -255,11 +258,16 @@
 			printf(": can't map I/O space\n");
 			return;
 		}
-		/* Map PLX. */
-		if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO, PCI_MAPREG_TYPE_IO, 0,
-		    &plxt, &plxh, NULL, NULL) != 0) {
-			printf(": can't map PLX\n");
-			return;
+
+		if (wpp->wpp_plx == CHIP_PLX_OTHER) {
+			/* The PLX 9052 doesn't have IO at 0x14.  Perhaps
+			   other chips have, so we'll make this conditional. */
+			if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO,
+				PCI_MAPREG_TYPE_IO, 0, &plxt,
+				&plxh, NULL, NULL) != 0) {
+					printf(": can't map PLX\n");
+					return;
+				}
 		}
 	} else {
 		if (pci_mapreg_map(pa, WI_PCI_CBMA,
@@ -294,7 +302,7 @@
 	CSR_WRITE_2(sc, WI_INT_EN, 0);
 	CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
 
-	if (wpp->wpp_plx) {
+	if (wpp->wpp_plx == CHIP_PLX_OTHER) {
 		uint32_t command;
 #define	WI_LOCAL_INTCSR		0x4c
 #define	WI_LOCAL_INTEN		0x40	/* poke this into INTCSR */


	
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