Subject: Re: port-sparc/20962: Recently updated ss20/hs sparc/mp stops with
To: None <gnats-bugs@gnats.netbsd.org>
From: Havard Eidnes <he@netbsd.org>
List: netbsd-bugs
Date: 05/18/2003 10:13:30
Hi,
this bug is still with me with recently-updated-to 1.6T.
The spot indicated by the console's ctrace is the same as before:
NetBSD/sparc (grizzly.urc.uninett.no) (console)
login: May 17 10:30:03 grizzly su: he to root on /dev/ttyp1
xcall(cpu1,0xf026ba88): couldn't ping cpus, cpuset=1
xcall(cpu1,0xf026ba88): couldn't ping cpus, cpuset=1
Asyv
Watchdog Reset
Type help for more information
<#2> ok nmi_hard: SMP botch.cpu0: NMI: system interrupts: 90000<VME=0,SBUS=0,E,T>
Level 15 Interrupt
<#2> ok ctrace
PC: f026bca0
Last leaf: call 10042cfc from 10042a80
0 w %o0-%o5: ( 0 ffffffe0 24 f0002000 200 20 )
jmpl f026bc28 from f0229f40
1 w %o0-%o5: ( a 0 24 0 f5d02000 20000000 )
call f0229dc4 from f026c0e8
2 w %o0-%o5: ( f026bc28 a 4 1 1 1 )
jmpl f026c0cc from f026b56c
3 w %o0-%o5: ( a 4 24 f026c0cc 3f000 2 )
call f026b534 from f026c740
4 w %o0-%o5: ( a 4 2 f6b7d000 2 f05dd9f0 )
call f026c5cc from f027d168
5 w %o0-%o5: ( 0 f6b7efb0 0 45ec ffffffff 805 )
call f027ce9c from f0008694
6 w %o0-%o5: ( 25 1e000082 10042d70 f6b7efb0 0 3e000 )
XXXXXXX from 54ff4
7 w %o0-%o5: ( 3040873 81c06174 3000000 81c06000 10ea4 91 )
call 13f70 from 13a8c
8 w %o0-%o5: ( 3f1b0 2 13a88 3ec00 3e000 0 )
call 13970 from 13a48
9 w %o0-%o5: ( 3f1b0 2 13a10 3f000 42040 27 )
call 13970 from 1392c
a w %o0-%o5: ( 43234 0 1f8 3e000 3f000 2 )
call 13908 from 1e564
b w %o0-%o5: ( 3f000 0 0 3e000 3f000 2 )
call 1e224 from 11adc
c w %o0-%o5: ( 3e090 effff2c4 effff2d4 10 1 10049270 )
call 11a18 from 11a08
d w %o0-%o5: ( 3 effff2c4 3e000 10043a9c 1005e000 effffff0 )
(gdb) x/i 0xf026bca0
0xf026bca0 <srmmu_cache_flush+120>: sta %o0, [ %l0 ] #ASI_AIUP
(gdb) x/i 0xf0229f40
0xf0229f40 <xcall+380>: call %i0
(gdb) x/i 0xf026c0e8
0xf026c0e8 <smp_cache_flush+28>: call 0xf0229dc4 <xcall>
(gdb) x/i 0xf026b56c
0xf026b56c <cache_flush+56>: call %o3
(gdb) x/i 0xf026c740
0xf026c740 <emulinstr+372>: call 0xf026b534 <cache_flush>
(gdb) x/i 0xf027d168
0xf027d168 <trap+716>: call 0xf026c5cc <emulinstr>
(gdb) x/i 0xf0008694
0xf0008694 <Lslowtrap_reenter+56>: call 0xf027ce9c <trap>
(gdb)
<#2> ok .psr
CWP: 4 ET: 1 PS: 1 S: 1 PIL: b EF: 0 EC: 0 ICC: nZvC VER: e IMPL: 1
<#2> ok .registers
%g0 %g1 %g2 %g3 %g4 %g5 %g6 %g7
0 8000000 2 f084af90 3e800 ffffffff f6b7d000 f026c65c
PC nPC Y PSR WIM TBR
f026bca0 f026bca4 8000 1e500be4 8 f0006090
<#2> ok .locals
0 1 2 3 4 5 6 7
IN: a 0 24 0 f5d02000 20000000 f6b7ece8 f0229f40
LOC: 0 13be4 13934 4 0 300 f6b7d000 1023f380
OUT: 0 ffffffe0 24 f0002000 200 20 f6b7ec80 10042a80
<#2> ok 0 .window
0 1 2 3 4 5 6 7
IN: a 0 24 0 f5d02000 20000000 f6b7ece8 f0229f40
LOC: 0 13be4 13934 4 0 300 f6b7d000 1023f380
OUT: 0 ffffffe0 24 f0002000 200 20 f6b7ec80 10042a80
<#2> ok 1 .window
0 1 2 3 4 5 6 7
IN: f026bc28 a 4 1 1 1 f6b7ed58 f026c0e8
LOC: 2 f0002058 f0342000 f0342000 0 f0303800 f6b7ef20 1023f380
OUT: a 0 24 0 f5d02000 20000000 f6b7ece8 f0229f40
<#2> ok 2 .window
0 1 2 3 4 5 6 7
IN: a 4 24 f026c0cc 3f000 2 f6b7edc0 f026b56c
LOC: effff130 3f434 1e4bc 8000 1 80 f6b7d000 0
OUT: f026bc28 a 4 1 1 1 f6b7ed58 f026c0e8
<#2> ok
(gdb) l srmmu_cache_flush
725 void
726 srmmu_cache_flush(base, len, ctx)
727 caddr_t base;
728 u_int len;
729 int ctx;
730 {
731 int i, ls, baseoff;
732 char *p;
733
734 if (len < PAGE_SIZE) {
(gdb) l
735 int octx;
736 /* less than a page, flush just the covered cache lines */
737 ls = CACHEINFO.c_linesize;
738 baseoff = (int)base & (ls - 1);
739 i = (baseoff + len + ls - 1) >> CACHEINFO.c_l2linesize;
740 p = (char *)((int)base & -ls);
741 octx = getcontext4m();
742 trapoff();
743 setcontext4m(ctx);
744 for (; --i >= 0; p += ls)
(gdb) l
745 sta(p, ASI_IDCACHELFP, 0);
746 #if defined(MULTIPROCESSOR)
747 if (cpuinfo.cpu_type == CPUTYP_HS_MBUS) {
748 /*
749 * See hypersparc comment in srmmu_vcache_flush_page().
750 * Just flush both possibly touched pages
751 * fromt the TLB.
752 */
753 int va = (int)base & ~0xfff;
754 sta(va | ASI_SRMMUFP_L3, ASI_SRMMUFP, 0);
(gdb) i li *0xf026bca0
Line 745 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bca0 <srmmu_cache_flush+120>
and ends at 0xf026bca4 <srmmu_cache_flush+124>.
(gdb) x/10i
0xf026bca0 <srmmu_cache_flush+120>: sta %o0, [ %l0 ] #ASI_AIUP
0xf026bca4 <srmmu_cache_flush+124>: addcc %i1, -1, %i1
0xf026bca8 <srmmu_cache_flush+128>:
bpos 0xf026bca0 <srmmu_cache_flush+120>
0xf026bcac <srmmu_cache_flush+132>: add %l0, %o5, %l0
0xf026bcb0 <srmmu_cache_flush+136>: sethi %hi(0xf0002000), %o0
0xf026bcb4 <srmmu_cache_flush+140>:
ld [ %o0 + 0x17c ], %o1 ! 0xf000217c
0xf026bcb8 <srmmu_cache_flush+144>: cmp %o1, 0x1a
0xf026bcbc <srmmu_cache_flush+148>: bne 0xf026bcdc <srmmu_cache_flush+180>
0xf026bcc0 <srmmu_cache_flush+152>: mov 0x200, %o1
0xf026bcc4 <srmmu_cache_flush+156>: and %i0, -4096, %o0
(gdb)
(gdb) i li 737
Line 737 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bc44 <srmmu_cache_flush+28>
and ends at 0xf026bc48 <srmmu_cache_flush+32>.
(gdb) x/10i
0xf026bc44 <srmmu_cache_flush+28>: ld [ %o3 + 0x90 ], %o5 ! 0xf0002090
0xf026bc48 <srmmu_cache_flush+32>: mov 0x200, %o4
0xf026bc4c <srmmu_cache_flush+36>: add %o5, -1, %o1
0xf026bc50 <srmmu_cache_flush+40>: and %i0, %o1, %l0
0xf026bc54 <srmmu_cache_flush+44>: add %l0, %l3, %o0
0xf026bc58 <srmmu_cache_flush+48>: add %o0, %o5, %o0
0xf026bc5c <srmmu_cache_flush+52>: ld [ %o3 + 0x94 ], %o2
0xf026bc60 <srmmu_cache_flush+56>: add %o0, -1, %o0
0xf026bc64 <srmmu_cache_flush+60>: neg %o5, %o1
0xf026bc68 <srmmu_cache_flush+64>: srl %o0, %o2, %i1
(gdb) x/10i
0xf026bc6c <srmmu_cache_flush+68>: and %i0, %o1, %l0
0xf026bc70 <srmmu_cache_flush+72>: lda [ %o4 ] #ASI_N, %o2
0xf026bc74 <srmmu_cache_flush+76>: rd %psr, %o0
0xf026bc78 <srmmu_cache_flush+80>: and %o0, -33, %o0
0xf026bc7c <srmmu_cache_flush+84>: mov %o0, %psr
0xf026bc80 <srmmu_cache_flush+88>: nop
0xf026bc84 <srmmu_cache_flush+92>: nop
0xf026bc88 <srmmu_cache_flush+96>: nop
0xf026bc8c <srmmu_cache_flush+100>: mov 0x200, %o0 ! 0x200
0xf026bc90 <srmmu_cache_flush+104>: sta %i2, [ %o0 ] #ASI_N
(gdb) x/10i
0xf026bc94 <srmmu_cache_flush+108>: addcc %i1, -1, %i1
0xf026bc98 <srmmu_cache_flush+112>:
bneg 0xf026bcb0 <srmmu_cache_flush+136>
0xf026bc9c <srmmu_cache_flush+116>: clr %o0
0xf026bca0 <srmmu_cache_flush+120>: sta %o0, [ %l0 ] #ASI_AIUP
0xf026bca4 <srmmu_cache_flush+124>: addcc %i1, -1, %i1
0xf026bca8 <srmmu_cache_flush+128>:
bpos 0xf026bca0 <srmmu_cache_flush+120>
0xf026bcac <srmmu_cache_flush+132>: add %l0, %o5, %l0
0xf026bcb0 <srmmu_cache_flush+136>: sethi %hi(0xf0002000), %o0
0xf026bcb4 <srmmu_cache_flush+140>:
ld [ %o0 + 0x17c ], %o1 ! 0xf000217c
0xf026bcb8 <srmmu_cache_flush+144>: cmp %o1, 0x1a
(gdb)
(gdb) i li 738
Line 738 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bc4c <srmmu_cache_flush+36>
and ends at 0xf026bc54 <srmmu_cache_flush+44>.
(gdb) i li 739
Line 739 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bc54 <srmmu_cache_flush+44>
and ends at 0xf026bc64 <srmmu_cache_flush+60>.
(gdb) i li 740
Line 740 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bc64 <srmmu_cache_flush+60>
and ends at 0xf026bc68 <srmmu_cache_flush+64>.
(gdb) i li 741
Line 741 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bc48 <srmmu_cache_flush+32>
and ends at 0xf026bc4c <srmmu_cache_flush+36>.
(gdb) i li 742
Line 742 of "/usr/src/sys/arch/sparc/sparc/cache.c"
is at address 0xf026bc8c <srmmu_cache_flush+100> but contains no code.
(gdb) i li 743
Line 743 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bc8c <srmmu_cache_flush+100>
and ends at 0xf026bc94 <srmmu_cache_flush+108>.
(gdb) i li 744
Line 744 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bc94 <srmmu_cache_flush+108>
and ends at 0xf026bca0 <srmmu_cache_flush+120>.
(gdb) i li 745
Line 745 of "/usr/src/sys/arch/sparc/sparc/cache.c"
starts at address 0xf026bca0 <srmmu_cache_flush+120>
and ends at 0xf026bca4 <srmmu_cache_flush+124>.
(gdb) i li 746
Line 746 of "/usr/src/sys/arch/sparc/sparc/cache.c"
is at address 0xf026bcb0 <srmmu_cache_flush+136> but contains no code.
(gdb)
Now, it would seem to me that "p" as stored in %l0 is zero, at the
same time "i" is also zero in %i1. This despite the "base" argument
probably being 0xa (as observed further down in the register window),
something which puzzles me.
Other than that someone more aware of the sparc architecture than me
needs to have a closer look at this.
Regards,
- Havard