dan@pod51.demon.co.uk wrote:
    > A suitable fix would be to alter line 833 (of revision 1.91) to say:
    >
    > if (status & EHCI_QTD_HALTED) {


    This fix seems wrong given that the HALTED bit can be masked
    away on line 801.
    I'm curious, what are the errors that you have observed that
    the host controller recovers from?


Line 801 only masks HALTED if it's the last one and complete, not for 
intermediate transfers or short reads.

The host controller can recover from up to 3 errors on a given 
transaction. We are developing some hardware which was causing a lot of 
XACTER and BUFERR errors, but they were getting through with the 
hardware retries.

I suspect the error rate in normal operation is not absolutely zero - 
there is quite possibly the odd transaction which has an error and has 
to get retried, but halting the pipe just because there was a retry 
could be a bit terminal.

If a transfer is not marked as NORMAL_COMPLETION when it has only 
suffered retries,. then further up the stack, it doesn't complete 
properly, especially if it is marked as IOERROR.

-- 
Daniel Ellis                     Conexant Systems Ltd
Senior Software Engineer         Unit 230 Cambridge Science Park
http://www.conexant.com          Milton Road
Phone: +44 1223 707318           Cambridge  CB4 0WB
Fax:   +44 1223 707447           UK





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