Subject: Re: port-evbmips/31992: alchemy ICU is too Au1000 specific
To: None <port-evbmips-maintainer@netbsd.org, gnats-admin@netbsd.org,>
From: Garrett D'Amore <garrett_damore@tadpole.com>
List: netbsd-bugs
Date: 11/03/2005 17:22:01
The following reply was made to PR port-evbmips/31992; it has been noted by GNATS.
From: "Garrett D'Amore" <garrett_damore@tadpole.com>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-evbmips/31992: alchemy ICU is too Au1000 specific
Date: Thu, 03 Nov 2005 09:19:12 -0800
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Index: au_icu.c
===================================================================
RCS file: /net/projects/meteor/cvs/netbsd/src/sys/arch/mips/alchemy/au_icu.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 au_icu.c
--- au_icu.c 29 Sep 2005 16:42:45 -0000 1.1.1.1
+++ au_icu.c 3 Nov 2005 17:16:25 -0000
@@ -37,10 +37,10 @@
*/
/*
- * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs.
+ * Interrupt support for the AMD Alchemy CPUs.
*
- * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal
- * interrupt controllers.
+ * The Alchemy's interrupts are wired to two internal interrupt
+ * controllers, providing up to 64 external IRQs.
*/
#include <sys/cdefs.h>
@@ -116,89 +116,89 @@
#define NIRQS 64
-const char *au1000_intrnames[NIRQS] = {
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "ssi0",
- "ssi1",
- "dma0",
- "dma1",
- "dma2",
- "dma3",
- "dma4",
- "dma5",
- "dma6",
- "dma7",
- "pc0",
- "pc0 match1",
- "pc0 match2",
- "pc0 match3",
- "pc1",
- "pc1 match1",
- "pc1 match2",
- "pc1 match3",
- "irda tx",
- "irda rx",
- "usb intr",
- "usb suspend",
- "usb host",
- "ac97",
- "mac0",
- "mac1",
- "i2s",
- "ac97 cmd",
-
- "gpio 0",
- "gpio 1",
- "gpio 2",
- "gpio 3",
- "gpio 4",
- "gpio 5",
- "gpio 6",
- "gpio 7",
- "gpio 8",
- "gpio 9",
- "gpio 10",
- "gpio 11",
- "gpio 12",
- "gpio 13",
- "gpio 14",
- "gpio 15",
- "gpio 16",
- "gpio 17",
- "gpio 18",
- "gpio 19",
- "gpio 20",
- "gpio 21",
- "gpio 22",
- "gpio 23",
- "gpio 24",
- "gpio 25",
- "gpio 26",
- "gpio 27",
- "gpio 28",
- "gpio 29",
- "gpio 30",
- "gpio 31",
+const char *au_icu_intrnames[NIRQS] = {
+ "irq 0",
+ "irq 1",
+ "irq 2",
+ "irq 3",
+ "irq 4",
+ "irq 5",
+ "irq 6",
+ "irq 7",
+ "irq 8",
+ "irq 9",
+ "irq 10",
+ "irq 11",
+ "irq 12",
+ "irq 13",
+ "irq 14",
+ "irq 15",
+ "irq 16",
+ "irq 17",
+ "irq 18",
+ "irq 19",
+ "irq 20",
+ "irq 21",
+ "irq 22",
+ "irq 23",
+ "irq 24",
+ "irq 25",
+ "irq 26",
+ "irq 27",
+ "irq 28",
+ "irq 29",
+ "irq 30",
+ "irq 31",
+
+ "irq 32",
+ "irq 33",
+ "irq 34",
+ "irq 35",
+ "irq 36",
+ "irq 37",
+ "irq 38",
+ "irq 39",
+ "irq 40",
+ "irq 41",
+ "irq 42",
+ "irq 43",
+ "irq 44",
+ "irq 45",
+ "irq 46",
+ "irq 47",
+ "irq 48",
+ "irq 49",
+ "irq 50",
+ "irq 51",
+ "irq 52",
+ "irq 53",
+ "irq 54",
+ "irq 55",
+ "irq 56",
+ "irq 57",
+ "irq 58",
+ "irq 59",
+ "irq 60",
+ "irq 61",
+ "irq 62",
+ "irq 63",
};
-struct au1000_intrhead {
+struct au_intrhead {
struct evcnt intr_count;
int intr_refcnt;
};
-struct au1000_intrhead au1000_intrtab[NIRQS];
+struct au_intrhead au_intrtab[NIRQS];
#define NINTRS 4 /* MIPS INT0 - INT3 */
-struct au1000_cpuintr {
+struct au_cpuintr {
LIST_HEAD(, evbmips_intrhand) cintr_list;
struct evcnt cintr_count;
};
-struct au1000_cpuintr au1000_cpuintrs[NINTRS];
-const char *au1000_cpuintrnames[NINTRS] = {
+struct au_cpuintr au_cpuintrs[NINTRS];
+const char *au_cpu_intrnames[NINTRS] = {
"icu 0, req 0",
"icu 0, req 1",
"icu 1, req 0",
@@ -211,17 +211,17 @@
int i;
for (i = 0; i < NINTRS; i++) {
- LIST_INIT(&au1000_cpuintrs[i].cintr_list);
- evcnt_attach_dynamic(&au1000_cpuintrs[i].cintr_count,
- EVCNT_TYPE_INTR, NULL, "mips", au1000_cpuintrnames[i]);
+ LIST_INIT(&au_cpuintrs[i].cintr_list);
+ evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count,
+ EVCNT_TYPE_INTR, NULL, "mips", au_cpu_intrnames[i]);
}
for (i = 0; i < NIRQS; i++) {
/* XXX steering - use an irqmap array? */
- au1000_intrtab[i].intr_refcnt = 0;
- evcnt_attach_dynamic(&au1000_intrtab[i].intr_count,
- EVCNT_TYPE_INTR, NULL, "au1000", au1000_intrnames[i]);
+ au_intrtab[i].intr_refcnt = 0;
+ evcnt_attach_dynamic(&au_intrtab[i].intr_count,
+ EVCNT_TYPE_INTR, NULL, "au_icu", au_icu_intrnames[i]);
}
}
@@ -254,12 +254,12 @@
* a list anyway) per irq, not per CPU interrupt?
*/
cpu_int = (irq < 32 ? 0 : 2);
- LIST_INSERT_HEAD(&au1000_cpuintrs[cpu_int].cintr_list, ih, ih_q);
+ LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q);
/*
* Now enable it.
*/
- if (au1000_intrtab[irq].intr_refcnt++ == 0) {
+ if (au_intrtab[irq].intr_refcnt++ == 0) {
icu_base = (irq < 32) ? IC0_BASE : IC1_BASE;
irq &= 31; /* throw away high bit if set */
@@ -325,7 +325,7 @@
* Now, disable it, if there is nothing remaining on the
* list.
*/
- if (au1000_intrtab[irq].intr_refcnt-- == 1) {
+ if (au_intrtab[irq].intr_refcnt-- == 1) {
icu_base = (irq < 32) ? IC0_BASE : IC1_BASE;
irq &= 31; /* throw away high bit if set */
@@ -385,11 +385,11 @@
irqmask = REGVAL(icu_base + IC_REQUEST1_INT);
break;
}
- au1000_cpuintrs[level].cintr_count.ev_count++;
- LIST_FOREACH(ih, &au1000_cpuintrs[level].cintr_list, ih_q) {
+ au_cpuintrs[level].cintr_count.ev_count++;
+ LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) {
/* XXX should check is see if interrupt is masked? */
if (1 << ih->ih_irq & irqmask) {
- au1000_intrtab[ih->ih_irq].intr_count.ev_count++;
+ au_intrtab[ih->ih_irq].intr_count.ev_count++;
(*ih->ih_func)(ih->ih_arg);
REGVAL(icu_base + IC_MASK_CLEAR) = 1 << ih->ih_irq;
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