>Number:         32216
>Category:       port-amd64
>Synopsis:       Missing HTT feature display for Opterons dual-core CPUs
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    port-amd64-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Fri Dec 02 16:14:00 +0000 2005
>Originator:     Nicolas Joly
>Release:        NetBSD 3.99.13
>Organization:
Institut Pasteur, Paris.
>Environment:
System: NetBSD lanfeust.sis.pasteur.fr 3.99.13 NetBSD 3.99.13 (LANFEUST) #0: Wed Nov 30 11:04:07 CET 2005 njoly@lanfeust.sis.pasteur.fr:/local/src/NetBSD/obj/amd64/sys/arch/amd64/compile/LANFEUST amd64
Architecture: x86_64
Machine: amd64
>Description:
According to the AMD CPUID document (rev 2.16), There is a new
hyper-threading technology (HTT) bit, on Fn0000_0001:EDX bit 28.
And this bit is set, at least,on Opterons dual-core CPUs.

<URL:http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf>

Replacing `B28' with `HTT' in CPUID_EXT_FLAGS3 will give a better display:

cpu0: AMD Opteron(tm) Processor 865, 1804.21 MHz
cpu0: features: f7dbfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features: f7dbfbff<PGE,MCA,CMOV,PAT,PSE36,MPC,NOX,MMXX,MMX>
cpu0: features: f7dbfbff<FXSR,SSE,SSE2,B28,LONG,3DNOW2,3DNOW>
                                       ^^^
vs.

cpu0: AMD Opteron(tm) Processor 865, 1804.18 MHz
cpu0: features: f7dbfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features: f7dbfbff<PGE,MCA,CMOV,PAT,PSE36,MPC,NOX,MMXX,MMX>
cpu0: features: f7dbfbff<FXSR,SSE,SSE2,HTT,LONG,3DNOW2,3DNOW>
                                       ^^^
>How-To-Repeat:
Try to boot a machine with Opterons dual-core, and watch CPUs features.
>Fix:
Index: sys/arch/x86/include/specialreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/include/specialreg.h,v
retrieving revision 1.8
diff -u -r1.8 specialreg.h
--- sys/arch/x86/include/specialreg.h	21 Feb 2005 15:10:51 -0000	1.8
+++ sys/arch/x86/include/specialreg.h	2 Dec 2005 15:28:12 -0000
@@ -150,7 +150,7 @@
 
 #define CPUID_EXT_FLAGS2	"\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
 				    "\24MPC\25NOX\26B21\27MMXX\30MMX"
-#define CPUID_EXT_FLAGS3	"\20\31FXSR\32SSE\33SSE2\34B27\35B28\36LONG" \
+#define CPUID_EXT_FLAGS3	"\20\31FXSR\32SSE\33SSE2\34B27\35HTT\36LONG" \
 				    "\0373DNOW2\0403DNOW"
 
 /*