>  Ouch, the old code certainly is wrong.
>  Other pcmcia bridge drivers do the OE after the ~200 ms Vcc rising time,
>  i.e. between the
>  
>     pcic_delay(h, 200 + 1, "pccen1"); 
>  
>  and the negate RESET - could you test if that works for your case too?

YES It works OK.  Here's what I did....

	 * some machines require some more time to be settled
	 * (100ms is added here).
	 */
	pcic_delay(h, 200 + 1, "pccen1");

        /* XXXX Card should be ready so now turn on output enable */
        power |=  PCIC_PWRCTL_OE;
        pcic_write(h, PCIC_PWRCTL, power);

	/* negate RESET */
	intr |= PCIC_INTR_RESET;
	pcic_write(h, PCIC_INTR, intr);

	/*
	 * RESET Setup Time (Tsu (RESET)) = 20ms
	 */
	pcic_delay(h, 20, "pccen2");

        /* XXXX Card should be ready so now turn on output enable */
/*	power |=  PCIC_PWRCTL_OE;
        pcic_write(h, PCIC_PWRCTL, power);
*/

-----

>  Otherwise we probably would have to audit all pcmcia bridge drivers and
>  adapt them.

Looks like moving the PCIC_PWRCTL_OE might break the Ricoh and/or Vadem power
hacks.  Looks like that is why the OE was moved up.

It would certainly be safer to wait until after the reset setup time to enable
the card output.  The XI-325 powers up "ugly" but seems to reset OK.  If there is a
card that resets "ugly" then there could be problems again. 

Changing the PCMCIA interface code can be a can or worms.  OTOH moving the
OE in all of the PCMCIA bridge drivers might fix some obscure problems elsewhere.  

djb