jdolecek@NetBSD.org said:
> cpu0: unknown Core FSB_FREQ value 0 (0x41c80000) 

Very strange, a 0 is illegal according to Intel's manual
(Software developers manual, System programming part 2, Appendix B)

I've got a quite similar box, also with FSB667, and it is
recognized without error:
cpu0: Intel Core 2 (Merom) (686-class), 1995.09 MHz, id 0x6f6
[...]
cpu0: "Intel(R) Core(TM)2 CPU         T7200  @ 2.00GHz"
cpu0: I-cache 32 KB 64B/line 8-way, D-cache 32 KB 64B/line 8-way
cpu0: using thermal monitor 1
cpu0: Enhanced SpeedStep (1228 mV) 2000 MHz
cpu0: unknown Enhanced SpeedStep CPU.
cpu0: using only highest and lowest power states.
cpu0: Enhanced SpeedStep frequencies available (MHz): 2000 1000

(The L2 cache is not reported, which is probably easy to fix, and the est
code doesn't know details, which might be a larger issue, but this
is not related to the strange MSR reading.)

>                case 0:
>                        bus_clock = 6666;
>                        break;

This is very likely incorrect, as (a) the "0" shouldn't happen,
and (b) it would affect all Core/Core2 processors.

Are you using some non-default compiler optimisation?

best regards
Matthias