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Hi,

On Wed, Aug 29, 2007 at 02:45:02PM +0000, fujiwara@f.pyon.org wrote:

>  est_init_main: bus_clock = 10000
>  est_init_main: idlo = 0x607
>  est_init_main: lo   812 mV,  600 MHz
>  est_init_main: raw    7   ,    6    
>  est_init_main: idhi = 0x807
>  est_init_main: hi   812 mV,  800 MHz
>  est_init_main: raw    7   ,    8    
>  est_init_main: cur  = 0x807
>  est_init_main: fake entry 0:  812 mV,  800 MHz  MSR*100 mV =  700 freq =  800
>  est_init_main: fake entry 1:  812 mV,  600 MHz  MSR*100 mV =  700 freq =  600
>  cpu0: Enhanced SpeedStep frequencies available (MHz): 800 600

I'm guessing that your CPU should also support running at 700MHz.  Can
you try the attached patch instead of your original patch?  You can
verify that each frequency is different by setting them with
"sysctl -w machdep.powernow.frequency.target=<freq>" and then running
"openssl speed md2".  You should see differing performance for each
selected speed.

Thanks,
Simon.

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Index: est.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/est.c,v
retrieving revision 1.3
diff -d -p -u -r1.3 est.c
--- est.c	6 Aug 2007 03:38:49 -0000	1.3
+++ est.c	30 Aug 2007 11:16:45 -0000
@@ -1199,9 +1199,10 @@ est_init_main(int vendor)
 		maxvolt = MSR2VOLTINC(idhi);
 		freqinc = maxfreq - minfreq;
 		voltinc = maxvolt - minvolt;
-		if (freqinc < voltinc) {
+		if (freqinc < voltinc || voltinc == 0) {
 			tablesize = maxfreq - minfreq + 1;
-			voltinc = voltinc * 100 / freqinc - 1;
+			if (voltinc != 0)
+				voltinc = voltinc * 100 / freqinc - 1;
 			freqinc = 100;
 		} else {
 			tablesize = maxvolt - minvolt + 1;
@@ -1224,7 +1225,7 @@ est_init_main(int vendor)
 			    "MSR*100 mV = %4d freq = %4d\n",
 			    __FUNCTION__, j, MSR2MV(fake_table[j]),
 			    MSR2MHZ(fake_table[j], bus_clock),
-			    freq, volt);
+			    volt, freq);
 #endif /* EST_DEBUG */
 			freq -= freqinc;
 			volt -= voltinc;

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