Re: port-amd64/38480: x86 MTRR code makes invalid assumption of 8 variable MTRRs

[Thor Lancelot Simon <tls%rek.tjls.com@localhost>]

The following reply was made to PR port-amd64/38480; it has been noted by GNATS.

From: Thor Lancelot Simon <tls%rek.tjls.com@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc: port-amd64-maintainer%netbsd.org@localhost, 
gnats-admin%netbsd.org@localhost,
        netbsd-bugs%netbsd.org@localhost, tls%NetBSD.ORG@localhost, 
ad%netbsd.org@localhost
Subject: Re: port-amd64/38480: x86 MTRR code makes invalid assumption of 8 
variable MTRRs
Date: Sat, 26 Apr 2008 11:02:26 -0400

 This is -- obliquely -- described in the architecture manual, part 3A,
 (Intel document 253668) chapter 10, section 10.11.  This section has
 clearly been repeatedly revised -- it's got typos, and references to
 it in other parts of the document sometimes get the section number
 wrong...
 
 Now, watch out!  Evidently, newer processors -- such as the one I have --
 are not really, quite, "Pentium 4, Intel Xeon, and P6 family processors"
 in this regard, as you might guess from the fact that many other datasheets
 and spec updates on the Intel site break out the Core and subsequent
 processors separately (e.g. there's a whole separate set of spec updates
 for "800 Mhz bus Xeon" processors); clearly, there are processors out there,
 made by Intel, where "the IA32_MTRRCAP MSR always contains the value 508H"
 is not so, and I've got one.
 
 It looks like it should always be safe to read (and rely on) VCNT; but
 assuming there are always 8 is no longer safe.
 
 Anyway, 10.11.1 "MTRR Feature Identification" says:
 
 The availability of the MTRR feature is model-specific. Software can determine
 if MTRRs are supported on a processor by executing the CPUID instruction and
 reading the state of the MTRR flag (bit 12) in the feature information
 register (EDX).
 
 If the MTRR flag is set (indicating that the processor implements MTRRs),
 additional information about MTRRs can be obtained from the 64-bit
 IA32_MTRRCAP MSR (named MTRRcap MSR for the P6 family processors). The
 IA32_MTRRCAP MSR is a read-only MSR that can be read with the RDMSR
 instruction. Figure 10-4 shows the contents of the IA32_MTRRCAP MSR. The
 functions of the flags and field in this register are as follows:
 
 *      VCNT (variable range registers count) field, bits 0 through 7 --
                Indicates the number of variable ranges implemented on the
                processor. The Pentium 4, Intel Xeon, and P6 family processors
                have eight pairs of MTRRs for setting up eight variable ranges.
 
 *      FIX (fixed range registers supported) flag, bit 8 -- Fixed
                range MTRRs (IA32_MTRR_FIX64K_00000 through
                IA32_MTRR_FIX4K_0F8000) are supported when set; no fixed
                range registers are supported when clear.
 
 *      WC (write combining) flag, bit 10 -- The write-combining
        (WC) memory type is supported when set; the WC type is not
        supported when clear.
 
 Bit 9 and bits 11 through 63 in the IA32_MTRRCAP MSR are reserved.
 If software attempts to write to the IA32_MTRRCAP MSR, a general-protection
 exception (#GP) is generated.
 
 For the Pentium 4, Intel Xeon, and P6 family processors, the IA32_MTRRCAP MSR
 always contains the value 508H.