kern/38704: AMD_L3_CACHE info incorrect in x86/include/identcpu.h

[paul%whooppee.com@localhost]

>Number:         38704
>Category:       kern
>Synopsis:       AMD_L3_CACHE info incorrect in x86/include/identcpu.h
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    kern-bug-people
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Tue May 20 13:25:02 +0000 2008
>Originator:     Paul Goyette
>Release:        NetBSD 4.99.62
>Organization:
----------------------------------------------------------------------
|   Paul Goyette   | PGP DSS Key fingerprint: |  E-mail addresses:   |
| Customer Service | FA29 0E3B 35AF E8AE 6651 |  paul%whooppee.com@localhost   |
| Network Engineer | 0786 F758 55DE 53BA 7731 | pgoyette%juniper.net@localhost |
----------------------------------------------------------------------
>Environment:
        
        
System: NetBSD quicky.whooppee.com 4.99.62 NetBSD 4.99.62 (QUICKY (ASUS M2N32 
WS) 2008-05-14 13:20:42) #1: Wed May 14 06:25:08 PDT 2008 
paul%speedy.whooppee.com@localhost:/build/obj/amd64/sys/arch/amd64/compile/QUICKY
 amd64
Architecture: x86_64
Machine: amd64
>Description:
According to AMD documentation, the L3 cache entries are measured in 512K
increments.  (Ref AMD publication 25481, page 19 at
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf
        
>How-To-Repeat:
        
>Fix:
Apply the following patch.

Index: src/sys/arch/x86/include/cacheinfo.h
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/include/cacheinfo.h,v
retrieving revision 1.6
diff -u -p -r1.6 cacheinfo.h
--- src/sys/arch/x86/include/cacheinfo.h        11 May 2008 21:19:17 -0000      
1.6
+++ src/sys/arch/x86/include/cacheinfo.h        20 May 2008 13:15:31 -0000
@@ -125,7 +125,7 @@ struct x86_cache_info {
 #define        AMD_L2_ECX_C_LS(x)               ( (x)        & 0xff)
 
 /* L3 Cache */
-#define AMD_L3_EDX_C_SIZE(x)           ((((x) >> 18) & 0xffff) * 1024)
+#define AMD_L3_EDX_C_SIZE(x)           ((((x) >> 18) & 0xffff) * 1024 * 512)
 #define AMD_L3_EDX_C_ASSOC(x)           (((x) >> 12) & 0xff)
 #define AMD_L3_EDX_C_LPT(x)             (((x) >> 8)  & 0xf)
 #define AMD_L3_EDX_C_LS(x)              ( (x)        & 0xff)

>Unformatted: