port-powerpc/41370: inline splx() and splraise() needs __insn_barrier()

[Manuel Bouyer <bouyer%antioche.eu.org@localhost>]

>Number:         41370
>Category:       port-powerpc
>Synopsis:       inline splx() and splraise() needs __insn_barrier()
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    port-powerpc-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Wed May 06 18:45:00 +0000 2009
>Originator:     Manuel Bouyer
>Release:        NetBSD 5.0
>Organization:
>Environment:
5.0_STABLE sources
Architecture: powerpc
Machine: powerpc
>Description:
        if splhigh() is an inline or macro, the compiler may optimise things
        wrongly around it. An example is softint_schedule(), where the
        second check for SOFTINT_PENDING is optimised out. See PR kern/38637
        for details.
        To avoid this, splraise(), spllower() and splx() should be a
        barrier for the compiler; in the case of inline powerpc version of
        these functions a __insn_barrier() may be needed.

>How-To-Repeat:
        code inspection
>Fix:
        
Index: marvell/marvell_intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/marvell/marvell_intr.h,v
retrieving revision 1.15
diff -u -p -u -r1.15 marvell_intr.h
--- marvell/marvell_intr.h      28 Apr 2008 20:23:32 -0000      1.15
+++ marvell/marvell_intr.h      6 May 2009 18:39:36 -0000
@@ -360,6 +360,7 @@ splraise(int ncpl)
                }
        }
         extintr_restore(omsr);
+       __insn_barrier();
         return (ocpl);
 }
 
@@ -370,6 +371,7 @@ splx(int xcpl)
        register_t omsr;
        int ncpl = xcpl & IPL_PRIMASK;
 
+       __insn_barrier();
        ncplp = &imask[ncpl];
 
        omsr = extintr_disable();
@@ -391,6 +393,7 @@ spllower(int ncpl)
        imask_t *ncplp;
        register_t omsr;
 
+       __insn_barrier();
        ncpl &= IPL_PRIMASK;
        ncplp = &imask[ncpl];