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Re: kern/36838 (pci bus is disabled on ACPI kernel on Fujitsu FMV LOOX P70WN.)
My report is not filed in GNATS.
I will send again.
From: Ryo ONODERA <ryo_on%yk.rim.or.jp@localhost>
Subject: Re: kern/36838 (pci bus is disabled on ACPI kernel on Fujitsu FMV LOOX
P70WN.)
Date: Tue, 02 Mar 2010 23:04:54 +0900 (JST)
> Hi,
>
> I applied following 2 patches and investigated what disable pci2.
>
> First, for pci_probe_device() in src/sys/dev/pci/pci.c .
>
> --- pci.c.orig 2010-03-01 18:51:36.000000000 +0900
> +++ pci.c 2010-03-02 21:28:47.000000000 +0900
> @@ -315,10 +315,13 @@
> * as appropriate.
> */
> pa.pa_flags = sc->sc_flags;
> + aprint_verbose("Before: csr = 0x%08x, pa.pa_flags = 0x%04x, pa.pa_bus =
> 0x%04x\n", csr, pa.pa_flags, pa.pa_bus);
> if ((csr & PCI_COMMAND_IO_ENABLE) == 0)
> pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED;
> + aprint_verbose("After:IO: csr = 0x%08x, pa.pa_flags = 0x%04x, pa.pa_bus
> = 0x%04x\n", csr, pa.pa_flags, pa.pa_bus);
> if ((csr & PCI_COMMAND_MEM_ENABLE) == 0)
> pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED;
> + aprint_verbose("After:MEM: csr = 0x%08x, pa.pa_flags = 0x%04x,
> pa.pa_bus = 0x%04x\n", csr, pa.pa_flags, pa.pa_bus);
>
> /*
> * If the cache line size is not configured, then
>
>
>
>
> Second, for pci_conf_read() in src/sys/arch/x86/pci/pci_machdep.c .
>
> --- pci_machdep.c.orig 2010-03-01 18:53:17.000000000 +0900
> +++ pci_machdep.c 2010-03-02 21:58:51.000000000 +0900
> @@ -409,8 +409,10 @@
>
> KASSERT((reg & 0x3) == 0);
>
> - if (pc != NULL && pc->pc_conf_read != NULL)
> + if (pc != NULL && pc->pc_conf_read != NULL) {
> + aprint_verbose("RETURN from NULL check\n");
> return (*pc->pc_conf_read)(pc, tag, reg);
> + }
>
> #if defined(__i386__) && defined(XBOX)
> if (arch_i386_is_xbox) {
>
>
>
>
> I attach two dmesg, one is enabled ACPI (dmesg-csr-ACPI), and another is
> disabled ACPI (dmesg-csr-NOACPI).
>
> In ACPI-enabled dmesg, pci_conf_read() returns 0x00100000.
> But in ACPI-disabled dmesg, pci_conf_read() returns 0x00100007.
>
> Line 291, csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); exists in
> pci_probe_device()
> in src/sys/dev/pci/pci.c, and the code
>
> /*
> * Set up memory, I/O enable, and PCI command flags
> * as appropriate.
> */
> pa.pa_flags = sc->sc_flags;
> if ((csr & PCI_COMMAND_IO_ENABLE) == 0)
> pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED;
> if ((csr & PCI_COMMAND_MEM_ENABLE) == 0)
> pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED;
>
> disables pci2 on my PC, I think.
> (0x00100000 & 0x01 is zero and 0x00100000 & 0x02 is zero.)
>
> But, the core of pci_conf_read() in src/sys/arch/x86/pci/pci_machdep.c is
> written in assembly language.
> I cannot understand what is done.
>
> Can anyone analyze it? I will offer all data about this issue.
>
>
> P.S.
> It seems that port-i386/42676 (http://gnats.netbsd.org/42676) is similar to
> my problem.
> In port-i386/42676, the machine uses same chipset and pci1 is disabled.
>
> --
> Ryo ONODERA // ryo_on%yk.rim.or.jp@localhost
> PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
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