port-alpha/50326: cosmetic (with fix): Pyxis ASIC pass must be revision + 1

[m4j0rd0m0%gmail.com@localhost]

>Number:         50326
>Category:       port-alpha
>Synopsis:       cosmetic (with fix): Pyxis ASIC pass must be revision + 1
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    port-alpha-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sat Oct 10 18:00:00 +0000 2015
>Originator:     Felix Deichmann
>Release:        7.0 daily 201510080600Z
>Organization:
>Environment:
NetBSD/alpha 7.0 daily 201510080600Z
>Description:
The message displaying Pyxis ASIC pass is wrong. SRM differs in showing it as cc_rev + 1, which was also correct in cia.c before revision 1.43:

>>>show config
                        Digital AlphaPC 164LX 599 MHz

SRM Console V5.8-1         OpenVMS PALcode V1.21-2, Digital UNIX PALcode V1.23-2

SROM Revision: 3.1.2
Alpha 21164A-2
Pyxis ASIC Pass 2
[...]


Entering netbsd.alpha.gz at 0xfffffc0000431220...
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 7.0 (INSTALL.201510080600Z)
Digital AlphaPC 164LX 599 MHz, s/n 
8192 byte page size, 1 processor.
total memory = 512 MB
(2128 KB reserved for PROM, 509 MB used by NetBSD)
avail memory = 492 MB
kern.module.path=/stand/alpha/7.0/modules
mainbus0 (root)
cpu0 at mainbus0: ID 0 (primary), 21164A-2
cpu0: Architecture extensions: 0x1<BWX>
cia0 at mainbus0: DECchip 2117x Core Logic Chipset (Pyxis), pass 1
cia0: extended capabilities: 0x1<BWEN>
cia0: using BWX for PCI config access
[...]
>How-To-Repeat:
Boot a system with Pyxis ASIC like Alpha PC 164LX.
>Fix:
--- src/sys/arch/alpha/pci/cia.c.r1.73	Sat Oct 10 19:41:41 2015
+++ src/sys/arch/alpha/pci/cia.c	Sat Oct 10 19:43:09 2015
@@ -284,11 +284,10 @@
 
 	if (ccp->cc_flags & CCF_ISPYXIS) {
 		name = "Pyxis";
-		pass = ccp->cc_rev;
 	} else {
 		name = "ALCOR/ALCOR2";
-		pass = ccp->cc_rev + 1;
 	}
+	pass = ccp->cc_rev + 1;
 
 	aprint_normal(": DECchip 2117x Core Logic Chipset (%s), pass %d\n",
 	    name, pass);