Re: kern/52468: ISA DMA incorrectly maps I/O port 0x80 for page address registers

[glitch <glitch%glitchwrks.com@localhost>]

The following reply was made to PR kern/52468; it has been noted by GNATS.

From: glitch <glitch%glitchwrks.com@localhost>
To: gnats-bugs%netbsd.org@localhost
Cc: 
Subject: Re: kern/52468: ISA DMA incorrectly maps I/O port 0x80 for page
 address registers
Date: Sun, 6 Aug 2017 22:36:39 -0400

 Updated patch, unified format against /usr per #netbsd talk preferences. This patch corrects the offsets for bus_space_read() and bus_space_write() in isadma.c -- tested that ISA DMA is actually working with a SoundBlaster 16 which uses ISA DMA for sound sample playback.
 
 Thanks to Riastradh from #netbsd on freenode for pointing out my omission, and suggesting some of the additional fixes in this patch.
 
 diff -uNr usr_orig/src/sys/dev/isa/isadma.c usr/src/sys/dev/isa/isadma.c
 --- usr_orig/src/sys/dev/isa/isadma.c	2010-11-13 08:52:03.000000000 -0500
 +++ usr/src/sys/dev/isa/isadma.c	2017-08-06 19:53:51.163023103 -0400
 @@ -53,15 +53,17 @@
  struct isa_mem *isa_mem_head;
  
  /*
 - * High byte of DMA address is stored in this DMAPG register for
 - * the Nth DMA channel.
 + * DMA Channel to Address Page Register mapping
 + *
 + * Low byte of the DMA Address Page Register is stored in this DMAPG register
 + * for the Nth DMA channel.
   */
 -static int dmapageport[2][4] = {
 -	{0x7, 0x3, 0x1, 0x2},
 -	{0xf, 0xb, 0x9, 0xa}
 +static const int dmapageport[2][4] = {
 +	{0x87, 0x83, 0x81, 0x82},
 +	{0x8f, 0x8b, 0x89, 0x8a}
  };
  
 -static u_int8_t dmamode[] = {
 +static const u_int8_t dmamode[] = {
  	/* write to device/read from device */
  	DMA37MD_READ | DMA37MD_SINGLE,
  	DMA37MD_WRITE | DMA37MD_SINGLE,
 @@ -169,7 +171,7 @@
  		if (bus_space_map(ids->ids_bst, IO_DMA2, DMA2_IOSIZE, 0,
  		    &ids->ids_dma2h))
  			panic("_isa_dmainit: unable to map DMA controller #2");
 -		if (bus_space_map(ids->ids_bst, IO_DMAPG, 0xf, 0,
 +		if (bus_space_map(ids->ids_bst, IO_DMAPG, DMAPG_IOSIZE, 0,
  		    &ids->ids_dmapgh))
  			panic("_isa_dmainit: unable to map DMA page registers");
  
 @@ -211,7 +213,7 @@
  	/*
  	 * Unmap the registers used by the ISA DMA controller.
  	 */
 -	bus_space_unmap(ids->ids_bst, ids->ids_dmapgh, 0xf);
 +	bus_space_unmap(ids->ids_bst, ids->ids_dmapgh, DMAPG_IOSIZE);
  	bus_space_unmap(ids->ids_bst, ids->ids_dma2h, DMA2_IOSIZE);
  	bus_space_unmap(ids->ids_bst, ids->ids_dma1h, DMA1_IOSIZE);
  
 @@ -430,7 +432,7 @@
  		/* send start address */
  		waport = DMA1_CHN(ochan);
  		bus_space_write_1(ids->ids_bst, ids->ids_dmapgh,
 -		    dmapageport[0][ochan], (dmaaddr >> 16) & 0xff);
 +		    dmapageport[0][ochan] - IO_DMAPG, (dmaaddr >> 16) & 0xff);
  		bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport,
  		    dmaaddr & 0xff);
  		bus_space_write_1(ids->ids_bst, ids->ids_dma1h, waport,
 @@ -449,7 +451,7 @@
  		/* send start address */
  		waport = DMA2_CHN(ochan);
  		bus_space_write_1(ids->ids_bst, ids->ids_dmapgh,
 -		    dmapageport[1][ochan], (dmaaddr >> 16) & 0xff);
 +		    dmapageport[1][ochan] - IO_DMAPG, (dmaaddr >> 16) & 0xff);
  		dmaaddr >>= 1;
  		bus_space_write_1(ids->ids_bst, ids->ids_dma2h, waport,
  		    dmaaddr & 0xff);
 diff -uNr usr_orig/src/sys/dev/isa/isadmareg.h usr/src/sys/dev/isa/isadmareg.h
 --- usr_orig/src/sys/dev/isa/isadmareg.h	2008-04-28 16:23:52.000000000 -0400
 +++ usr/src/sys/dev/isa/isadmareg.h	2017-08-06 17:43:47.508172970 -0400
 @@ -47,6 +47,10 @@
  #define	ISA_DMA_MAXSIZE_DEFAULT(chan)					\
  	(((chan) & 4) ? ISA_DMA_MAXSIZE_16BIT : ISA_DMA_MAXSIZE_8BIT)
  
 +/* DMA Page Address Registers size */
 +
 +#define	DMAPG_IOSIZE	(1*15)
 +
  /*
   * Register definitions for DMA controller 1 (channels 0..3):
   */
 diff -uNr usr_orig/src/sys/dev/isa/isareg.h usr/src/sys/dev/isa/isareg.h
 --- usr_orig/src/sys/dev/isa/isareg.h	2005-12-11 07:22:02.000000000 -0500
 +++ usr/src/sys/dev/isa/isareg.h	2017-08-06 16:30:10.000000000 -0400
 @@ -55,7 +55,7 @@
  #define	IO_PPI		0x061		/* Programmable Peripheral Interface */
  #define	IO_RTC		0x070		/* RTC */
  #define	IO_NMI		IO_RTC		/* NMI Control */
 -#define	IO_DMAPG	0x080		/* DMA Page Registers */
 +#define	IO_DMAPG	0x081		/* DMA Page Registers */
  #define	IO_ICU2		0x0A0		/* 8259A Interrupt Controller #2 */
  #define	IO_DMA2		0x0C0		/* 8237A DMA Controller #2 */
  #define	IO_NPX		0x0F0		/* Numeric Coprocessor */