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Re: kern/42314: IC Plus IP100x PHY support
Hi,
Since, I have VIA EPIA-M900 motherboard with VT6130 Ethernet
controller and IP1001 phy, I made an effort to port OpenBSD driver,
and I prepared initial but not complete patch for PHY support (which
is almost a copy of OpenBSD driver with mainly small changes to cater
NetBSD specifics). Issues described below (first two I believe are
blocking from committing it to NetBSD yet and I need a help to resolve
if possible):
* For some reason direct port fails to work with autonegotation
(if_media match fails, there is no auto option available). As a
workaround I copied the code below from rgephy.c to add it manually
and it worked for me:
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
#define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", "
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA);
sep =", ";
PRINT("auto");
I believe it is a hack in this case, since OpenBSD seemingly doesn't
need it but for some reason direct port looses auto option in NetBSD.
Maybe somebody have idea, why it happened?
* Commented out the code with stge revision check in ipgphy_reset
(which calls also commented ipgphy_load_dspcode). I guess to implement
that I would need to change if_stge driver to move struct into a
header file or find another way to get sc_rev. Can someone help me out
with that?
* I change config for amd64 GENERIC only. I quite certain, it can be
added at least to i386, though OpenBSD defined it in most ports.
* Same as OpenBSD, manual setting to 1000baseT will fail,
autonegotation must be used to get Gigabit Ethernet speed.
* OUI in NetBSD is recognized as 0x0009c3, not as 0x0090c3 like it is
defined in Open/FreeBSD. Changed it in miidevs.
Attached the patch below (regen is still needed for miidevs).
With provided changes, vge successfully auto negotiated for 1Gbit
speed (which wasn't the case with general phy):
vge0: flags=0x8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> mtu 1500
capabilities=3f00<IP4CSUM_Rx,IP4CSUM_Tx,TCP4CSUM_Rx,TCP4CSUM_Tx>
capabilities=3f00<UDP4CSUM_Rx,UDP4CSUM_Tx>
enabled=0
ec_capabilities=7<VLAN_MTU,VLAN_HWTAGGING,JUMBO_MTU>
ec_enabled=2<VLAN_HWTAGGING>
address: xx:xx:xx:xx:xx:xx
media: Ethernet autoselect (1000baseT
full-duplex,flowcontrol,master,rxpause,txpause)
status: active
inet 192.168.1.18/24 broadcast 192.168.1.255 flags 0x0
inet6 fe80::8c9e:c8a0:eb4b:731f%vge0/64 flags 0x0 scopeid 0x
from dmesg:
ipgphy0 at vge0 phy 22: IP1001 10/100/1000 PHY, rev. 025
10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
P.S. Not sure if original submitter did provide a patch as well but
his link is down currently.
Regards,
Andrius V
On Sat, Nov 14, 2009 at 12:00 AM <tharada%oucrc.org@localhost> wrote:
>
> >Number: 42314
> >Category: kern
> >Synopsis: IC Plus IP100x PHY support
> >Confidential: no
> >Severity: non-critical
> >Priority: low
> >Responsible: kern-bug-people
> >State: open
> >Class: sw-bug
> >Submitter-Id: net
> >Arrival-Date: Fri Nov 13 22:00:00 +0000 2009
> >Originator: Tomokazu HARADA
> >Release: 5.99.22
> >Organization:
> >Environment:
> NetBSD xjazz 5.99.22 NetBSD 5.99.22 (GENERIC) #1: Sat Nov 14 06:05:25 JST 2009 root@xjazz:/usr/obj/sys/arch/i386/compile/GENERIC i386
>
> >Description:
> IC Plus IP1000A/IP1001 10/100/1000 PHY support
> (from OpenBSD ipgphy)
>
> vge0 at pci2 dev 0 function 0: VIA VT612X Gigabit Ethernet (rev. 0x82)
> vge0: interrupting at ioapic0 pin 16
> vge0: Ethernet address: 00:02:2a:e6:d7:ad
> ipgphy0 at vge0 phy 22: IP1001 10/100/1000 PHY, rev. 0
> ipgphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
>
> This is a VIA VT6130 PCIe GbE, the phy is integrated on.
>
> >How-To-Repeat:
> N/A
> >Fix:
> http://tharada.oucrc.org/ipgphy/
>
ADDED share/man/man4/ipgphy.4
Index: share/man/man4/ipgphy.4
==================================================================
--- share/man/man4/ipgphy.4
+++ share/man/man4/ipgphy.4
@@ -0,0 +1,38 @@
+.\" $OpenBSD: ipgphy.4,v 1.5 2009/08/08 17:12:40 naddy Exp $
+.\"
+.\" $NetBSD: ipgphy.4$
+.\"
+.\" Copyright (c) 2006 Brad Smith <brad%openbsd.org@localhost>
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate: August 8 2009 $
+.Dt IPGPHY 4
+.Os
+.Sh NAME
+.Nm ipgphy
+.Nd IC Plus IP1000A/IP1001 10/100/Gigabit Ethernet PHY
+.Sh SYNOPSIS
+.Cd "ipgphy* at mii?"
+.Sh DESCRIPTION
+The
+.Nm
+driver supports the IC Plus IP1000A/IP1001 10/100/Gigabit Ethernet PHY
+interface.
+.Sh SEE ALSO
+.Xr ifmedia 4 ,
+.Xr intro 4 ,
+.Xr mii 4 ,
+.Xr stge 4,
+.Xr vge 4,
+.Xr ifconfig 8
Index: sys/arch/amd64/conf/GENERIC
==================================================================
--- sys/arch/amd64/conf/GENERIC
+++ sys/arch/amd64/conf/GENERIC
@@ -871,10 +871,11 @@
igphy* at mii? phy ? # Intel IGP01E1000
ihphy* at mii? phy ? # Intel 82577 PHYs
ikphy* at mii? phy ? # Intel 82563 PHYs
inphy* at mii? phy ? # Intel 82555 PHYs
iophy* at mii? phy ? # Intel 82553 PHYs
+ipgphy* at mii? phy ? # IC PLUS IP1000A/IP1001 PHYs
lxtphy* at mii? phy ? # Level One LXT-970 PHYs
makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs
nsphy* at mii? phy ? # NS83840 PHYs
nsphyter* at mii? phy ? # NS83843 PHYs
pnaphy* at mii? phy ? # generic HomePNA PHYs
Index: sys/dev/DEVNAMES
==================================================================
--- sys/dev/DEVNAMES
+++ sys/dev/DEVNAMES
@@ -657,10 +657,11 @@
iopl MI
iopsp MI
ipaqbus hpcarm
ipaqlcd hpcarm
ipaqpcic hpcarm
+ipgphy MI
ipmi amd64
ipmi i386
ipmi xen
ipw MI
irdasir MI Attribute
Index: sys/dev/mii/files.mii
==================================================================
--- sys/dev/mii/files.mii
+++ sys/dev/mii/files.mii
@@ -97,10 +97,14 @@
device ikphy: mii_phy
attach ikphy at mii
file dev/mii/ikphy.c ikphy
+device ipgphy: mii_phy
+attach ipgphy at mii
+file dev/mii/ipgphy.c ipgphy
+
device sqphy: mii_phy
attach sqphy at mii
file dev/mii/sqphy.c sqphy
device tqphy: mii_phy
ADDED sys/dev/mii/ipgphy.c
Index: sys/dev/mii/ipgphy.c
==================================================================
--- sys/dev/mii/ipgphy.c
+++ sys/dev/mii/ipgphy.c
@@ -0,0 +1,423 @@
+/* $OpenBSD: ipgphy.c,v 1.19 2015/07/19 06:28:12 yuo Exp $ */
+
+/*-
+ * Copyright (c) 2006, Pyun YongHyeon <yongari%FreeBSD.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Driver for the IC Plus IP1000A/IP1001 10/100/1000 PHY.
+ */
+#include <sys/cdefs.h>
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+
+#include <dev/mii/ipgphyreg.h>
+
+#include <dev/pci/if_stgereg.h>
+
+static int ipgphy_match(device_t, cfdata_t, void *);
+static void ipgphy_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(ipgphy, sizeof(struct mii_softc),
+ ipgphy_match, ipgphy_attach, mii_phy_detach, mii_phy_activate);
+
+static int ipgphy_service(struct mii_softc *, struct mii_data *, int);
+static void ipgphy_status(struct mii_softc *);
+static int ipgphy_mii_phy_auto(struct mii_softc *);
+//static void ipgphy_load_dspcode(struct mii_softc *);
+static void ipgphy_reset(struct mii_softc *);
+
+static const struct mii_phy_funcs ipgphy_funcs = {
+ ipgphy_service, ipgphy_status, ipgphy_reset,
+};
+
+static const struct mii_phydesc ipgphys[] = {
+ MII_PHY_DESC(ICPLUS, IP1000A),
+ MII_PHY_DESC(ICPLUS, IP1001),
+ MII_PHY_END,
+};
+
+static int
+ipgphy_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct mii_attach_args *ma = aux;
+
+ if (mii_phy_match(ma, ipgphys) != NULL) {
+ return 10;
+ }
+ return 0;
+}
+
+static void
+ipgphy_attach(device_t parent, device_t self, void *aux)
+{
+ struct mii_softc *sc = device_private(self);
+ struct mii_attach_args *ma = aux;
+ struct mii_data *mii = ma->mii_data;
+ const struct mii_phydesc *mpd;
+ const char *sep = "";
+
+ mpd = mii_phy_match(ma, ipgphys);
+ aprint_naive(": Media interface\n");
+ aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
+
+ sc->mii_dev = self;
+ sc->mii_inst = mii->mii_instance;
+ sc->mii_phy = ma->mii_phyno;
+ sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
+ sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
+ sc->mii_mpd_rev = MII_REV(ma->mii_id2);
+ sc->mii_funcs = &ipgphy_funcs;
+ sc->mii_pdata = mii;
+ sc->mii_flags = ma->mii_flags;
+
+ sc->mii_flags |= MIIF_NOISOLATE;
+ sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+
+ PHY_RESET(sc);
+
+ PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
+ sc->mii_capabilities &= ma->mii_capmask;
+ sc->mii_capabilities &= ~BMSR_ANEG;
+ if (sc->mii_capabilities & BMSR_EXTSTAT)
+ PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
+
+ mii_phy_add_media(sc);
+
+#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
+#define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", "
+
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA);
+ sep =", ";
+ PRINT("auto");
+
+ aprint_normal("\n");
+}
+
+static int
+ipgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+ struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+ uint16_t gig, reg, speed;
+
+ switch (cmd) {
+ case MII_POLLSTAT:
+ /*
+ * If we're not polling our PHY instance, just return.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+ return 0;
+ break;
+
+ case MII_MEDIACHG:
+ /*
+ * If the media indicates a different PHY instance,
+ * isolate ourselves.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+ PHY_READ(sc, MII_BMCR, ®);
+ PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+ return 0;
+ }
+
+ /*
+ * If the interface is not up, don't do anything.
+ */
+ if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+ break;
+
+ PHY_RESET(sc);
+
+ switch (IFM_SUBTYPE(ife->ifm_media)) {
+ case IFM_AUTO:
+ (void)ipgphy_mii_phy_auto(sc);
+ goto done;
+ break;
+
+ case IFM_1000_T:
+ /*
+ * XXX
+ * Manual 1000baseT setting doesn't seem to work.
+ */
+ speed = BMCR_S1000;
+ break;
+
+ case IFM_100_TX:
+ speed = BMCR_S100;
+ break;
+
+ case IFM_10_T:
+ speed = BMCR_S10;
+ break;
+
+ default:
+ return EINVAL;
+ }
+
+ if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
+ speed |= BMCR_FDX;
+ gig = GTCR_ADV_1000TFDX;
+ } else
+ gig = GTCR_ADV_1000THDX;
+
+ PHY_WRITE(sc, MII_100T2CR, 0);
+ PHY_WRITE(sc, MII_BMCR, speed);
+
+ if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
+ break;
+
+ PHY_WRITE(sc, MII_100T2CR, gig);
+ PHY_WRITE(sc, MII_BMCR, speed);
+
+ if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
+ gig |= GTCR_MAN_MS | GTCR_ADV_MS;
+
+ PHY_WRITE(sc, MII_100T2CR, gig);
+
+done:
+ break;
+
+ case MII_TICK:
+ /*
+ * If we're not currently selected, just return.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+ return 0;
+
+ /*
+ * Is the interface even up?
+ */
+ if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+ return 0;
+
+ /*
+ * Only used for autonegotiation.
+ */
+ if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+ sc->mii_ticks = 0;
+ break;
+ }
+
+ /*
+ * Check to see if we have link. If we do, we don't
+ * need to restart the autonegotiation process. Read
+ * the BMSR twice in case it's latched.
+ */
+ PHY_READ(sc, MII_BMSR, ®);
+ PHY_READ(sc, MII_BMSR, ®);
+ if (reg & BMSR_LINK) {
+ /*
+ * Reset autonegotiation timer to 0 in case the link
+ * goes down in the next tick.
+ */
+ sc->mii_ticks = 0;
+ /* See above. */
+ break;
+ }
+
+ /* Announce link loss right after it happens */
+ if (sc->mii_ticks++ == 0)
+ break;
+
+ /*
+ * Only retry autonegotiation every mii_anegticks seconds.
+ */
+ if (sc->mii_ticks <= sc->mii_anegticks)
+ break;
+
+ sc->mii_ticks = 0;
+ ipgphy_mii_phy_auto(sc);
+ break;
+ }
+
+ /* Update the media status. */
+ ipgphy_status(sc);
+
+ /* Callback if something changed. */
+ mii_phy_update(sc, cmd);
+ return 0;
+}
+
+static void
+ipgphy_status(struct mii_softc *sc)
+{
+ struct mii_data *mii = sc->mii_pdata;
+ struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+ uint16_t bmsr, bmcr, stat, gtsr;
+
+ mii->mii_media_status = IFM_AVALID;
+ mii->mii_media_active = IFM_ETHER;
+
+ PHY_READ(sc, MII_BMSR, &bmsr);
+ PHY_READ(sc, MII_BMSR, &bmsr);
+ if (bmsr & BMSR_LINK)
+ mii->mii_media_status |= IFM_ACTIVE;
+
+ PHY_READ(sc, MII_BMCR, &bmcr);
+ if (bmcr & BMCR_LOOP)
+ mii->mii_media_active |= IFM_LOOP;
+
+ if (bmcr & BMCR_AUTOEN) {
+ if ((bmsr & BMSR_ACOMP) == 0) {
+ /* Erg, still trying, I guess... */
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+
+ if (sc->mii_mpd_model == MII_MODEL_ICPLUS_IP1001) {
+ PHY_READ(sc, IPGPHY_LSR, &stat);
+ switch (stat & IPGPHY_LSR_SPEED_MASK) {
+ case IPGPHY_LSR_SPEED_10:
+ mii->mii_media_active |= IFM_10_T;
+ break;
+ case IPGPHY_LSR_SPEED_100:
+ mii->mii_media_active |= IFM_100_TX;
+ break;
+ case IPGPHY_LSR_SPEED_1000:
+ mii->mii_media_active |= IFM_1000_T;
+ break;
+ default:
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+
+ if (stat & IPGPHY_LSR_FULL_DUPLEX)
+ mii->mii_media_active |= IFM_FDX;
+ else
+ mii->mii_media_active |= IFM_HDX;
+ } else {
+ PHY_READ(sc, STGE_PhyCtrl, &stat);
+ switch (PC_LinkSpeed(stat)) {
+ case PC_LinkSpeed_Down:
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ case PC_LinkSpeed_10:
+ mii->mii_media_active |= IFM_10_T;
+ break;
+ case PC_LinkSpeed_100:
+ mii->mii_media_active |= IFM_100_TX;
+ break;
+ case PC_LinkSpeed_1000:
+ mii->mii_media_active |= IFM_1000_T;
+ break;
+ default:
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+
+ if (stat & PC_PhyDuplexStatus)
+ mii->mii_media_active |= IFM_FDX;
+ else
+ mii->mii_media_active |= IFM_HDX;
+ }
+
+ if (mii->mii_media_active & IFM_FDX)
+ mii->mii_media_active |= mii_phy_flowstatus(sc);
+
+ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
+ PHY_READ(sc, MII_100T2SR, >sr);
+ if (gtsr & GTSR_MS_RES)
+ mii->mii_media_active |= IFM_ETH_MASTER;
+ }
+ } else
+ mii->mii_media_active = ife->ifm_media;
+}
+
+static int
+ipgphy_mii_phy_auto(struct mii_softc *sc)
+{
+ uint16_t reg = 0;
+
+ if (sc->mii_mpd_model == MII_MODEL_ICPLUS_IP1001) {
+ PHY_READ(sc, MII_ANAR, ®);
+ reg &= ~(ANAR_PAUSE_SYM | ANAR_PAUSE_ASYM);
+ reg |= ANAR_NP;
+ }
+
+ reg |= ANAR_10 | ANAR_10_FD | ANAR_TX | ANAR_TX_FD;
+
+ if (sc->mii_flags & MIIF_DOPAUSE)
+ reg |= ANAR_PAUSE_SYM | ANAR_PAUSE_ASYM;
+
+ PHY_WRITE(sc, MII_ANAR, reg | ANAR_CSMA);
+
+ reg = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+ if (sc->mii_mpd_model != MII_MODEL_ICPLUS_IP1001)
+ reg |= GTCR_ADV_MS;
+ PHY_WRITE(sc, MII_100T2CR, reg);
+
+ PHY_WRITE(sc, MII_BMCR, BMCR_FDX | BMCR_AUTOEN | BMCR_STARTNEG);
+
+ return EJUSTRETURN;
+}
+
+/*static void
+ipgphy_load_dspcode(struct mii_softc *sc)
+{
+ PHY_WRITE(sc, 31, 0x0001);
+ PHY_WRITE(sc, 27, 0x01e0);
+ PHY_WRITE(sc, 31, 0x0002);
+ PHY_WRITE(sc, 27, 0xeb8e);
+ PHY_WRITE(sc, 31, 0x0000);
+ PHY_WRITE(sc, 30, 0x005e);
+ PHY_WRITE(sc, 9, 0x0700);
+
+ DELAY(50);
+}*/
+
+static void
+ipgphy_reset(struct mii_softc *sc)
+{
+ //struct ifnet *ifp = sc->mii_pdata->mii_ifp;
+ uint16_t reg;
+
+ mii_phy_reset(sc);
+
+ /* clear autoneg/full-duplex as we don't want it after reset */
+ PHY_READ(sc, MII_BMCR, ®);
+ reg &= ~(BMCR_AUTOEN | BMCR_FDX);
+ PHY_WRITE(sc, MII_BMCR, reg);
+
+ /*if (sc->mii_mpd_model == MII_MODEL_ICPLUS_IP1000A &&
+ strcmp(ifp->if_xname, "stge") == 0) {
+ struct stge_softc *stge_sc = ifp->if_softc;
+ if (stge_sc->sc_rev >= 0x40 && stge_sc->sc_rev <= 0x4e)
+ ipgphy_load_dspcode(sc);
+ }*/
+}
ADDED sys/dev/mii/ipgphyreg.h
Index: sys/dev/mii/ipgphyreg.h
==================================================================
--- sys/dev/mii/ipgphyreg.h
+++ sys/dev/mii/ipgphyreg.h
@@ -0,0 +1,83 @@
+/* $OpenBSD: ipgphyreg.h,v 1.3 2015/07/19 06:28:12 yuo Exp $ */
+
+/*-
+ * Copyright (c) 2006, Pyun YongHyeon
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef _DEV_MII_IPGPHYREG_H_
+#define _DEV_MII_IPGPHYREG_H_
+
+/*
+ * Registers for the IC Plus IPGA internal PHY.
+ */
+
+/* PHY specific control & status register. IP1001 only. */
+#define IPGPHY_SCSR 0x10
+#define IPGPHY_SCSR_RXPHASE_SEL 0x0001
+#define IPGPHY_SCSR_TXPHASE_SEL 0x0002
+#define IPGPHY_SCSR_REPEATOR_MODE 0x0004
+#define IPGPHY_SCSR_RESERVED1_DEF 0x0008
+#define IPGPHY_SCSR_RXCLK_DRV_MASK 0x0060
+#define IPGPHY_SCSR_RXCLK_DRV_DEF 0x0040
+#define IPGPHY_SCSR_RXD_DRV_MASK 0x0180
+#define IPGPHY_SCSR_RXD_DRV_DEF 0x0100
+#define IPGPHY_SCSR_JABBER_ENB 0x0200
+#define IPGPHY_SCSR_HEART_BEAT_ENB 0x0400
+#define IPGPHY_SCSR_DOWNSHIFT_ENB 0x0800
+#define IPGPHY_SCSR_RESERVED2_DEF 0x1000
+#define IPGPHY_SCSR_LED_DRV_4MA 0x0000
+#define IPGPHY_SCSR_LED_DRV_8MA 0x2000
+#define IPGPHY_SCSR_LED_MODE_MASK 0xC000
+#define IPGPHY_SCSR_LED_MODE_DEF 0x0000
+
+/* PHY link status register. IP1001 only. */
+#define IPGPHY_LSR 0x11
+#define IPGPHY_LSR_JABBER_DET 0x0200
+#define IPGPHY_LSR_APS_SLEEP 0x0400
+#define IPGPHY_LSR_MDIX 0x0800
+#define IPGPHY_LSR_FULL_DUPLEX 0x1000
+#define IPGPHY_LSR_SPEED_10 0x0000
+#define IPGPHY_LSR_SPEED_100 0x2000
+#define IPGPHY_LSR_SPEED_1000 0x4000
+#define IPGPHY_LSR_SPEED_MASK 0x6000
+#define IPGPHY_LSR_LINKUP 0x8000
+
+/* PHY specific control register 2. IP1001 only. */
+#define IPGPHY_SCR
+#define IPGPHY_SCR_SEW_RATE_MASK 0x0003
+#define IPGPHY_SCR_SEW_RATE_DEF 0x0003
+#define IPGPHY_SCR_AUTO_XOVER 0x0004
+#define IPGPHY_SCR_SPEED_10_100_ENB 0x0040
+#define IPGPHY_SCR_FIFO_LATENCY_2 0x0000
+#define IPGPHY_SCR_FIFO_LATENCY_3 0x0080
+#define IPGPHY_SCR_FIFO_LATENCY_4 0x0100
+#define IPGPHY_SCR_FIFO_LATENCY_5 0x0180
+#define IPGPHY_SCR_MDIX_ENB 0x0200
+#define IPGPHY_SCR_RESERVED_DEF 0x0400
+#define IPGPHY_SCR_APS_ON 0x0800
+
+#endif /* _DEV_MII_IPGPHYREG_H_ */
Index: sys/dev/mii/miidevs
==================================================================
--- sys/dev/mii/miidevs
+++ sys/dev/mii/miidevs
@@ -74,11 +74,11 @@
oui MARVELL 0x005043 Marvell Semiconductor
oui QUALSEMI 0x006051 Quality Semiconductor
oui AMLOGIC 0x006051 Amlogic
oui DAVICOM 0x00606e Davicom Semiconductor
oui SMSC 0x00800f SMSC
-oui ICPLUS 0x0090c3 IC Plus Corp.
+oui ICPLUS 0x0009c3 IC Plus Corp.
oui SEEQ 0x00a07d Seeq
oui ICS 0x00a0be Integrated Circuit Systems
oui INTEL 0x00aa00 Intel
oui TSC 0x00c039 TDK Semiconductor
oui MYSON 0x00c0b4 Myson Technology
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