port-sparc/57515: sparc32 GCC defaults to SC memory ordering, which is not true on SPARCv8 processors

[koachan+netbsd%protonmail.com@localhost]

>Number:         57515
>Category:       port-sparc
>Synopsis:       sparc32 GCC defaults to SC memory ordering, which is not true on SPARCv8 processors
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    port-sparc-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sat Jul 08 16:10:00 +0000 2023
>Originator:     Koakuma
>Release:        9.3
>Organization:
N/A
>Environment:
NetBSD nbsd 9.3 NetBSD 9.3 (GENERIC.MP) #0: Thu Aug 4 15:30:37 UTC 2022 mkrepro%mkrepro.NetBSD.org@localhost:/usr/src/sys/arch/sparc/compile/GENERIC.MP sparc
>Description:
Currently, when targeting sparc32 processors, GCC assumes that the hardware has sequentially consistent memory ordering by default.
This can cause problems when running generated binaries on v8 and later processors, which uses weaker TSO ordering, because GCC does not emit the necessary barrier instructions for ordering.

Upstream report: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110592
>How-To-Repeat:
Compile this C++ code with `-O2`:
```
#include <atomic>

long load(std::atomic<long> ptr) {
    return ptr.load();
}

void store(std::atomic<long> ptr, long val) {
    ptr.store(val);
}
```

It should generate necessary `ldstub` barrier instructions, as shown here (on the -mcpu=v8 window): https://godbolt.org/z/oq8nnK6Th
But currently, unless -mcpu=v8 is passed explicitly, NetBSD's bundled GCC does not generate that.
>Fix:
N/A