PR/59327 CVS commit: src/tests/kernel

["Taylor R Campbell" <riastradh%netbsd.org@localhost>]

The following reply was made to PR kern/59327; it has been noted by GNATS.

From: "Taylor R Campbell" <riastradh%netbsd.org@localhost>
To: gnats-bugs%gnats.NetBSD.org@localhost
Cc: 
Subject: PR/59327 CVS commit: src/tests/kernel
Date: Mon, 21 Apr 2025 03:47:32 +0000

 Module Name:	src
 Committed By:	riastradh
 Date:		Mon Apr 21 03:47:32 UTC 2025
 
 Modified Files:
 	src/tests/kernel: t_signal_and_sp.c
 	src/tests/kernel/arch/mips: threadspfunc.S
 
 Log Message:
 t_signal_and_sp: Fix threadspfunc on mips.
 
 1. Writing branch delay slots requires `.set noreorder'.  Got used to
    reading and writing RISCy code with branch delay slots ages ago,
    still haven't gotten used to having to tell the assembler `no, I
    really want you to assemble the instructions I wrote, as I wrote
    them, and not some other instructions in some other order'.
 
 2. Return value is v0 on mips, not a0 like modern mips^W^Wriscv.
 
 With this, the threadsp test passes on mips.
 
 PR kern/59327: user stack pointer is not aligned properly
 
 
 To generate a diff of this commit:
 cvs rdiff -u -r1.7 -r1.8 src/tests/kernel/t_signal_and_sp.c
 cvs rdiff -u -r1.1 -r1.2 src/tests/kernel/arch/mips/threadspfunc.S
 
 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.