Re: ath0: cannot map register space

[Mayuresh <mayuresh%acm.org@localhost>]

On Sun, Feb 14, 2016 at 08:56:10AM +0100, Martin Husemann wrote:
> On Sun, Feb 14, 2016 at 11:14:42AM +0530, Mayuresh wrote:
> > ath0 at pci2 dev 0 function 0: Atheros 5424/2424
> > ath0: cannot map register space
> 
> Can you show output of "pcictl dump" for that device?

PCI configuration registers:
  Common header:
    0x00: 0x001c168c 0x00100006 0x02000001 0x00000010

    Vendor Name: Atheros Communications (0x168c)
    Device Name: AR5424 (0x001c)
    Command register: 0x0006
      I/O space accesses: off
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x0010
      Interrupt status: inactive
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: fast (0x0)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: network (0x02)
    Subclass Name: ethernet (0x00)
    Interface: 0x00
    Revision ID: 0x01
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x00
    Cache Line Size: 64bytes (0x10)

  Type 0 ("normal" device) header:
    0x10: 0x00000004 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00005001 0x04281468
    0x30: 0x00000000 0x00000040 0x00000000 0x0000010b

    Base address register at 0x10
      type: 64-bit nonprefetchable memory
      base: 0x0000000000000000, not sized
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00005001
    Subsystem vendor ID: 0x1468
    Subsystem ID: 0x0428
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x40
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x0b

  Capability register at 0x40
    type: 0x01 (Power Management)
  Capability register at 0x50
    type: 0x05 (MSI)
  Capability register at 0x60
    type: 0x10 (PCI Express)
  Capability register at 0x90
    type: 0x11 (MSI-X)

  PCI Power Management Capabilities Register
    Capabilities register: 0x41c2
      Version: 1.1
      PME# clock: off
      Device specific initialization: off
      3.3V auxiliary current: 375 mA
      D1 power management state support: off
      D2 power management state support: off
      PME# support D0: off
      PME# support D1: off
      PME# support D2: off
      PME# support D3 hot: on
      PME# support D3 cold: off
    Control/status register: 0x0000
      Power state: D0
      PCI Express reserved: off
      No soft reset: off
      PME# assertion: disabled
      PME# status: off
    Bridge Support Extensions register: 0x00
      B2/B3 support: off
      Bus Power/Clock Control Enable: off
    Data register: 0x00

  PCI Message Signaled Interrupt
    Message Control register: 0x0000
      MSI Enabled: off
      Multiple Message Capable: no (1 vector)
      Multiple Message Enabled: off (1 vector)
      64 Bit Address Capable: off
      Per-Vector Masking Capable: off
    Message Address register: 0x00000000
    Message Data register: 0x00000000

  PCI Express Capabilities Register
    Capability register: 0011
      Capability version: 1
      Device type: Legacy PCI Express Endpoint device
      Slot implemented: off
      Interrupt Message Number: 0
    Device Capabilities Register: 0x05040cc0
      Max Payload Size Supported: 128 bytes max
      Phantom Functions Supported: not available
      Extended Tag Field Supported: 5bit
      Endpoint L0 Acceptable Latency: 256ns to less than 512ns
      Endpoint L1 Acceptable Latency: 32us - 64us
      Attention Button Present: off
      Attention Indicator Present: off
      Power Indicator Present: off
      Role-Based Error Report: off
      Captured Slot Power Limit Value: 65
      Captured Slot Power Limit Scale: 1
      Function-Level Reset Capability: off
    Device Control Register: 0x2010
      Correctable Error Reporting Enable: off
      Non Fatal Error Reporting Enable: off
      Fatal Error Reporting Enable: off
      Unsupported Request Reporting Enable: off
      Enable Relaxed Ordering: on
      Max Payload Size: 128 byte
      Extended Tag Field Enable: off
      Phantom Functions Enable: off
      Aux Power PM Enable: off
      Enable No Snoop: off
      Max Read Request Size: 512 byte
    Device Status Register: 0x000a
      Correctable Error Detected: off
      Non Fatal Error Detected: on
      Fatal Error Detected: off
      Unsupported Request Detected: on
      Aux Power Detected: off
      Transaction Pending: off
    Link Capabilities Register: 0x00033c11
      Maximum Link Speed: 2.5GT/s
      Maximum Link Width: x1 lanes
      Active State PM Support: L0s and L1 supported
      L0 Exit Latency: 256ns to less than 512ns
      L1 Exit Latency: 32us - 64us
      Port Number: 0
      Clock Power Management: off
      Surprise Down Error Report: off
      Data Link Layer Link Active: off
      Link BW Notification Capable: off
      ASPM Optionally Compliance: off
    Link Control Register: 0x0048
      Active State PM Control: disabled
      Read Completion Boundary Control: 128bytes
      Link Disable: off
      Retrain Link: off
      Common Clock Configuration: on
      Extended Synch: off
      Enable Clock Power Management: off
      Hardware Autonomous Width Disable: off
      Link Bandwidth Management Interrupt Enable: off
      Link Autonomous Bandwidth Interrupt Enable: off
    Link Status Register: 0x1011
      Negotiated Link Speed: 2.5GT/s
      Negotiated Link Width: x1 lanes
      Training Error: off
      Link Training: off
      Slot Clock Configuration: on
      Data Link Layer Link Active: off
      Link Bandwidth Management Status: off
      Link Autonomous Bandwidth Status: off

  MSI-X Capability Register
    Message Control register: 0x0000
      Table Size: 1
      Function Mask: off
      MSI-X Enable: off
    Table offset register: 0x00000000
      Table offset: 00000000
      BIR: 0x0
    Pending bit array register: 0x00000000
      Pending bit array offset: 00000000
      BIR: 0x0

  Device-dependent header:
    0x40: 0x41c25001 0x00000000 0x00000000 0x00000000
    0x50: 0x00006005 0x00000000 0x00000000 0x00000000
    0x60: 0x00119010 0x05040cc0 0x000a2010 0x00033c11
    0x70: 0x10110048 0x00000000 0x000003c0 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000011 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000004 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000