Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Sat Aug  4 01:20:44 UTC 2001

Modified Files:
	pkgsrc/cad/verilog: Makefile distinfo
	pkgsrc/cad/verilog/patches: patch-ad
	pkgsrc/cad/verilog/pkg: PLIST
Removed Files:
	pkgsrc/cad/verilog/patches: patch-aa patch-ab patch-ac patch-ae

Log Message:
update to verilog-0.5

* The Big Change: VVP

Past versions of Icarus Verilog performed simulation by compiling the
Verilog design to intermediate C++ code, then in turn compiling that
C++ (usually with G++) to a binary executable. This program was then
executed to actually run the simulation.

The 0.5 compiler, however, uses a custom internal language called
"vvp." The vvp code generator writes a program in the vvp language
that the vvp interpreter executes. This gets runtime performance
similar to the older vvm method, but compile times are much faster.

The result of this change is that there is a new program, ``vvp'',
that is installed with the existing ``iverilog'' compiler. This
program actually executes the simulation generated by the vvp code
generator.

There are manual pages for the iverilog command and the new vvp
command, as well as a QUICK_START document to help you run your first
simulation.

* What Else Is New

The compiler itself is now a lot more robust. While it still does not
compile and understand the entire IEEE1364 standard, the compiler is
less likely to crash on bad input, gives better error messages, and
has generally been cleaned up.


To generate a diff of this commit:
cvs rdiff -r1.9 -r1.10 pkgsrc/cad/verilog/Makefile
cvs rdiff -r1.2 -r1.3 pkgsrc/cad/verilog/distinfo
cvs rdiff -r1.5 -r0 pkgsrc/cad/verilog/patches/patch-aa \
    pkgsrc/cad/verilog/patches/patch-ab pkgsrc/cad/verilog/patches/patch-ac
cvs rdiff -r1.5 -r1.6 pkgsrc/cad/verilog/patches/patch-ad
cvs rdiff -r1.4 -r0 pkgsrc/cad/verilog/patches/patch-ae
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog/pkg/PLIST

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.