Module Name:	pkgsrc
Committed By:	drochner
Date:		Wed Jan  5 15:20:10 UTC 2005

Modified Files:
	pkgsrc/cad/py-MyHDL: Makefile PLIST distinfo

Log Message:
update to 0.4.1
changes:
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes


To generate a diff of this commit:
cvs rdiff -r1.6 -r1.7 pkgsrc/cad/py-MyHDL/Makefile
cvs rdiff -r1.2 -r1.3 pkgsrc/cad/py-MyHDL/PLIST
cvs rdiff -r1.1.1.1 -r1.2 pkgsrc/cad/py-MyHDL/distinfo

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.