CVS commit: pkgsrc/emulators/qemu

["Nick Hudson" <skrll%netbsd.org@localhost>]

Module Name:    pkgsrc
Committed By:   skrll
Date:           Thu Apr 25 11:33:02 UTC 2019

Modified Files:
        pkgsrc/emulators/qemu: Makefile distinfo
Added Files:
        pkgsrc/emulators/qemu/patches: patch-target_hppa_insns.decode
            patch-target_hppa_mem__helper.c patch-target_hppa_translate.c

Log Message:
Add two fixes accepted upstream to support NetBSD/hppa


To generate a diff of this commit:
cvs rdiff -u -r1.203 -r1.204 pkgsrc/emulators/qemu/Makefile
cvs rdiff -u -r1.145 -r1.146 pkgsrc/emulators/qemu/distinfo
cvs rdiff -u -r0 -r1.1 \
    pkgsrc/emulators/qemu/patches/patch-target_hppa_insns.decode \
    pkgsrc/emulators/qemu/patches/patch-target_hppa_mem__helper.c \
    pkgsrc/emulators/qemu/patches/patch-target_hppa_translate.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: pkgsrc/emulators/qemu/Makefile
diff -u pkgsrc/emulators/qemu/Makefile:1.203 pkgsrc/emulators/qemu/Makefile:1.204
--- pkgsrc/emulators/qemu/Makefile:1.203        Thu Apr 25 07:32:53 2019
+++ pkgsrc/emulators/qemu/Makefile      Thu Apr 25 11:33:02 2019
@@ -1,7 +1,7 @@
-# $NetBSD: Makefile,v 1.203 2019/04/25 07:32:53 maya Exp $
+# $NetBSD: Makefile,v 1.204 2019/04/25 11:33:02 skrll Exp $
 
 DISTNAME=      qemu-4.0.0
-PKGREVISION=   1
+PKGREVISION=   2
 CATEGORIES=    emulators
 MASTER_SITES=  https://download.qemu.org/
 EXTRACT_SUFX=  .tar.xz

Index: pkgsrc/emulators/qemu/distinfo
diff -u pkgsrc/emulators/qemu/distinfo:1.145 pkgsrc/emulators/qemu/distinfo:1.146
--- pkgsrc/emulators/qemu/distinfo:1.145        Wed Apr 24 17:09:43 2019
+++ pkgsrc/emulators/qemu/distinfo      Thu Apr 25 11:33:02 2019
@@ -1,4 +1,4 @@
-$NetBSD: distinfo,v 1.145 2019/04/24 17:09:43 adam Exp $
+$NetBSD: distinfo,v 1.146 2019/04/25 11:33:02 skrll Exp $
 
 SHA1 (qemu-4.0.0.tar.xz) = 74cfb8f4724d9651fdd354560f2d291887b32cad
 RMD160 (qemu-4.0.0.tar.xz) = 58135f00c391823edce780d55a816f29dd73c34b
@@ -17,5 +17,8 @@ SHA1 (patch-hw_tpm_tpm__ioctl.h) = f99aa
 SHA1 (patch-hw_usb_dev-mtp.c) = c48e11fbe3a017f0e9f8dbd7bf46898b758ab79c
 SHA1 (patch-include_sysemu_kvm.h) = f99e8ad021f6c8e89e3ca52538bd9b0656e6f619
 SHA1 (patch-roms_u-boot_tools_imx8m__image.sh) = e4c452062f40569e33aa93eec4a65bd3af2e74fc
+SHA1 (patch-target_hppa_insns.decode) = 111ad3d5db1c46fd42bb033ac09db377303d352e
+SHA1 (patch-target_hppa_mem__helper.c) = 080d99b2a6dc7f5ab1df04ef6c316e5dcd133753
+SHA1 (patch-target_hppa_translate.c) = 8bdeaba3f19204ffd5465d33a44380bbcbfd7a57
 SHA1 (patch-target_i386_kvm-stub.c) = 4cd2b7a8d8d8a317829f982b5acff7fdf2479d9f
 SHA1 (patch-ui_curses.c) = 436815cb8cd679b8f86cbae6c5f070e6ff158a6d

Added files:

Index: pkgsrc/emulators/qemu/patches/patch-target_hppa_insns.decode
diff -u /dev/null pkgsrc/emulators/qemu/patches/patch-target_hppa_insns.decode:1.1
--- /dev/null   Thu Apr 25 11:33:02 2019
+++ pkgsrc/emulators/qemu/patches/patch-target_hppa_insns.decode        Thu Apr 25 11:33:02 2019
@@ -0,0 +1,14 @@
+$NetBSD: patch-target_hppa_insns.decode,v 1.1 2019/04/25 11:33:02 skrll Exp $
+
+--- target/hppa/insns.decode.orig      2019-04-23 18:14:46.000000000 +0000
++++ target/hppa/insns.decode
+@@ -133,6 +133,9 @@ ixtlbx          000001 b:5 r:5 sp:2 0100
+ ixtlbx          000001 b:5 r:5 ... 000000 addr:1 0 00000        \
+                 sp=%assemble_sr3x data=0
+ 
++# pcxl and pcxl2 Fast TLB Insert instructions
++ixtlbxf         000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
++
+ pxtlbx          000001 b:5 x:5 sp:2 0100100 local:1 m:1 -----   data=1
+ pxtlbx          000001 b:5 x:5 ... 000100 local:1 m:1 -----     \
+                 sp=%assemble_sr3x data=0
Index: pkgsrc/emulators/qemu/patches/patch-target_hppa_mem__helper.c
diff -u /dev/null pkgsrc/emulators/qemu/patches/patch-target_hppa_mem__helper.c:1.1
--- /dev/null   Thu Apr 25 11:33:02 2019
+++ pkgsrc/emulators/qemu/patches/patch-target_hppa_mem__helper.c       Thu Apr 25 11:33:02 2019
@@ -0,0 +1,14 @@
+$NetBSD: patch-target_hppa_mem__helper.c,v 1.1 2019/04/25 11:33:02 skrll Exp $
+
+--- target/hppa/mem_helper.c.orig      2019-04-23 18:14:46.000000000 +0000
++++ target/hppa/mem_helper.c
+@@ -154,8 +154,7 @@ int hppa_get_physical_address(CPUHPPASta
+ 
+     if (unlikely(!(prot & type))) {
+         /* The access isn't allowed -- Inst/Data Memory Protection Fault.  */
+-        ret = (type & PAGE_EXEC ? EXCP_IMP :
+-               prot & PAGE_READ ? EXCP_DMP : EXCP_DMAR);
++        ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR;
+         goto egress;
+     }
+ 
Index: pkgsrc/emulators/qemu/patches/patch-target_hppa_translate.c
diff -u /dev/null pkgsrc/emulators/qemu/patches/patch-target_hppa_translate.c:1.1
--- /dev/null   Thu Apr 25 11:33:02 2019
+++ pkgsrc/emulators/qemu/patches/patch-target_hppa_translate.c Thu Apr 25 11:33:02 2019
@@ -0,0 +1,63 @@
+$NetBSD: patch-target_hppa_translate.c,v 1.1 2019/04/25 11:33:02 skrll Exp $
+
+--- target/hppa/translate.c.orig       2019-04-23 18:14:46.000000000 +0000
++++ target/hppa/translate.c
+@@ -2518,6 +2518,58 @@ static bool trans_pxtlbx(DisasContext *c
+ #endif
+ }
+ 
++/* Implement the pcxl and pcxl2 Fast TLB Insert instructions.
++ * See
++ *     https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
++ *     page 13-9 (195/206) */
++static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
++{
++    CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
++#ifndef CONFIG_USER_ONLY
++    TCGv_tl addr;
++    TCGv_reg reg;
++    TCGv_reg ar, sr;
++    TCGv_tl atl, stl;
++
++    nullify_over(ctx);
++
++/*    if (not (pcxl or pcxl2))
++          return gen_illegal(ctx); */
++
++    ar = get_temp(ctx);
++    sr = get_temp(ctx);
++    atl = get_temp_tl(ctx);
++    stl = get_temp_tl(ctx);
++    addr = get_temp_tl(ctx);
++
++
++    if (a->data) {
++        tcg_gen_ld_reg(sr, cpu_env, offsetof(CPUHPPAState, cr[CR_ISR]));
++        tcg_gen_ld_reg(ar, cpu_env, offsetof(CPUHPPAState, cr[CR_IOR]));
++    } else {
++        tcg_gen_ld_reg(sr, cpu_env, offsetof(CPUHPPAState, cr[CR_IIASQ]));
++        tcg_gen_ld_reg(ar, cpu_env, offsetof(CPUHPPAState, cr[CR_IIAOQ]));
++    }
++
++    tcg_gen_extu_reg_tl(atl, ar);
++    tcg_gen_extu_reg_tl(stl, sr);
++    tcg_gen_shli_i64(stl, stl, 32);
++    tcg_gen_or_tl(addr, atl, stl);
++    reg = load_gpr(ctx, a->r);
++    if (a->addr) {
++        gen_helper_itlba(cpu_env, addr, reg);
++    } else {
++        gen_helper_itlbp(cpu_env, addr, reg);
++    }
++
++    /* Exit TB for TLB change if mmu is enabled.  */
++    if (ctx->tb_flags & PSW_C) {
++        ctx->base.is_jmp = DISAS_IAQ_N_STALE;
++    }
++    return nullify_end(ctx);
++#endif
++}
++
+ static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
+ {
+     CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);