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uhd: Drop, older than ham/uhd
Module Name: pkgsrc-wip
Committed By: Kamil Rytarowski <n54%gmx.com@localhost>
Pushed By: kamil
Date: Wed Sep 21 01:38:58 2016 +0200
Changeset: f9cf754a0702b8951022840af39c1c2a26d52584
Removed Files:
uhd/DESCR
uhd/MESSAGES
uhd/Makefile
uhd/PLIST
uhd/PLIST.doxygen
uhd/PLIST.manual
uhd/TODO
uhd/buildlink3.mk
uhd/distinfo
uhd/options.mk
uhd/patches/patch-host_include_uhd_transport_nirio_nirio__driver__iface_h
Log Message:
uhd: Drop, older than ham/uhd
To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=f9cf754a0702b8951022840af39c1c2a26d52584
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
diffstat:
uhd/DESCR | 7 -
uhd/MESSAGES | 7 -
uhd/Makefile | 116 -
uhd/PLIST | 3998 --------------------
uhd/PLIST.doxygen | 820 ----
uhd/PLIST.manual | 48 -
uhd/TODO | 39 -
uhd/buildlink3.mk | 12 -
uhd/distinfo | 6 -
uhd/options.mk | 17 -
...lude_uhd_transport_nirio_nirio__driver__iface_h | 24 -
11 files changed, 5094 deletions(-)
diffs:
diff --git a/uhd/DESCR b/uhd/DESCR
deleted file mode 100644
index 830dcfe..0000000
--- a/uhd/DESCR
+++ /dev/null
@@ -1,7 +0,0 @@
-UHD is the free & open-source software driver and API for the
-Universal Software Radio Peripheral (USRP(TM)) SDR platform,
-created and sold by Ettus Research, LLC.
-
-UHD supports all Ettus Research USRP(TM) hardware, including
-all motherboards and daughterboards, and the combinations
-thereof.
diff --git a/uhd/MESSAGES b/uhd/MESSAGES
deleted file mode 100644
index e00835d..0000000
--- a/uhd/MESSAGES
+++ /dev/null
@@ -1,7 +0,0 @@
-===========================================================================
-$NetBSD: MESSAGES,v 1.1 2014/09/06 05:23:28 makoto Exp $
-Following directories are installed under ${PREFIX}/share/uhd
- firmware Source code for all microprocessors in USRP hardware
- fpga Source code for the UHD FPGA images
- images Package builder for FPGA and firmware images
-===========================================================================
diff --git a/uhd/Makefile b/uhd/Makefile
deleted file mode 100644
index 270c240..0000000
--- a/uhd/Makefile
+++ /dev/null
@@ -1,116 +0,0 @@
-# $NetBSD: Makefile,v 1.9 2014/10/04 12:40:17 makoto Exp $
-
-DISTNAME= 003_007_003_rc1
-#DISTNAME= uhd-images_003.007.003-rc1
-PKGNAME= uhd-3.7.3rc1
-CATEGORIES= ham
-MASTER_SITE= https://github.com/EttusResearch/uhd/archive
-#MASTER_SITE+= http://files.ettus.com/binaries/maint_images/archive
-EXTRACT_SUFX= .zip
-DIST_SUBDIR= uhd
-
-MAINTAINER= pkgsrc-users%NetBSD.org@localhost
-HOMEPAGE= http://code.ettus.com/redmine/ettus/projects/uhd/wiki
-COMMENT= USRP (Universal Software Radio Peripheral) Hardware Drivers
-LICENSE= gnu-gpl-v2
-
-BUILD_DEPENDS+= ${PYPKGPREFIX}-cheetah-[0-9]*:../../devel/py-cheetah
-
-USE_LANGUAGES= c c++
-USE_TOOLS= cmake pkg-config
-USE_CMAKE= yes
-
-# Please note distribution has many stuff under uhd/, but build itself
-# needs under host/ only. Those uhd/ stuff will be handled post-{patch,install}:
-WRKSRC= ${WRKDIR}/uhd-${DISTNAME}/host
-
-
-# The files with their name uhd-xxxx, are moved down from uhd/xxxx for this process.
-REPLACE_PYTHON= \
- utils/uhd_images_downloader.py.in \
- utils/usrp2_card_burner.py \
- utils/usrp2_card_burner_gui.py \
- utils/usrp_n2xx_net_burner.py \
- utils/usrp_n2xx_net_burner_gui.py \
- uhd-firmware/fx2/utils/build_eeprom.py \
- uhd-firmware/fx2/utils/edit-gpif-b100.py \
- uhd-firmware/fx2/utils/edit-gpif.py \
- uhd-firmware/fx2/utils/generate_regs.py \
- uhd-firmware/x300/bin_to_coe.py \
- uhd-firmware/zpu/bin/bin_to_mif.py \
- uhd-firmware/zpu/bin/bin_to_ram_macro_init.py \
- uhd-firmware/zpu/bin/divisors.py \
- uhd-firmware/zpu/bin/elf_to_sbf \
- uhd-firmware/zpu/bin/serial_loader \
- uhd-firmware/zpu/bin/uart_ihex_flash_loader.py \
- uhd-firmware/zpu/bin/uart_ihex_ram_loader.py \
- uhd-fpga/usrp1/gen_makefile_extra.py \
- uhd-fpga/usrp1/sdr_lib/gen_cordic_consts.py \
- uhd-fpga/usrp1/tb/makesine.pl \
- uhd-fpga/usrp1/toplevel/mrfm/mrfm.py \
- uhd-fpga/usrp1/toplevel/mrfm/mrfm_fft.py \
- uhd-fpga/usrp2/sdr_lib/gen_cordic_consts.py \
- uhd-fpga/usrp2/top/extract_usage.py \
- uhd-fpga/usrp2/top/python/check_inout.py \
- uhd-fpga/usrp2/top/python/check_timing.py \
- uhd-fpga/usrp3/top/python/bit_to_zynq_bin.py \
- uhd-fpga/usrp3/top/python/check_inout.py \
- uhd-fpga/usrp3/top/python/check_timing.py \
- uhd-fpga/usrp3/lib/io_port2/create-lvbitx.py \
-
-REPLACE_PERL= uhd-fpga/usrp1/tb/makesine.pl
-
-REPLACE_BASH= \
- uhd-fpga/usrp2/top/impactor.sh \
- uhd-fpga/usrp3/top/impactor.sh \
- uhd-fpga/usrp3/top/python/batch-build \
-
-INSTALLATION_DIRS+= share/uhd
-INSTALLATION_DIRS+= share/uhd/firmware
-INSTALLATION_DIRS+= share/uhd/fpga
-INSTALLATION_DIRS+= share/uhd/images
-
-SUBST_CLASSES+= man
-SUBST_MESSAGE.man= Convert share/man to man
-SUBST_STAGE.man= pre-configure
-SUBST_FILES.man= docs/CMakeLists.txt
-SUBST_SED.man= -e '/UHD_INSTALL/s,$${PKG_MAN_DIR},${PREFIX}/${PKGMANDIR}/man1,'
-# UHD_INSTALL(FILES ${gzfile} DESTINATION ${PKG_MAN_DIR} COMPONENT manpages)
-
-# is it default ? and redundent ?
-PLIST_SRC= ${PKGDIR}/PLIST
-.include "options.mk"
-
-# Copy (beyond) upper directory files (which should be handled at post-install)
-# to receive REPLACE_PYTHON conversion ( otherwise above the range )
-post-patch:
- (cd ${WRKDIR}; \
- for i in firmware fpga images ; do \
- ${MKDIR} ${WRKSRC}/uhd-$$i ;\
- ${CP} -r ${WRKDIR}/uhd-${DISTNAME}/$$i/* ${WRKSRC}/uhd-$$i ;\
- done)
-.include "options.mk"
-PKG_OPTIONS_VAR= PKG_OPTIONS.uhd
-PKG_SUPPORTED_OPTIONS= build-ninja
-PKG_SUGGESTED_OPTIONS=
-
-.include "../../mk/bsd.options.mk"
-
-# (1) move back the files to original location after REPLACE_PYTHON handled
-# (2) suppress warning at intallation, "non executable files get +x bit set".
-#
-# Converting ${CP} into ${INTALL_DATA_DIR} and ${INSTALL_DATA} as pkglint
-# flags are not easy, sorry for that.
-post-install:
- for i in firmware fpga images ; do \
- ${CP} -r ${WRKSRC}/uhd-$$i/* ${DESTDIR}${PREFIX}/share/uhd/$$i/;\
- ${FIND} ${DESTDIR}${PREFIX}/share/uhd/$$i -type f -exec \
- ${CHMOD} -x '{}' \; ;\
- done
-
-.include "../../lang/python/application.mk"
-.include "../../devel/boost-libs/buildlink3.mk"
-.include "../../devel/libusb1/buildlink3.mk"
-.include "../../devel/orc/buildlink3.mk"
-
-.include "../../mk/bsd.pkg.mk"
diff --git a/uhd/PLIST b/uhd/PLIST
deleted file mode 100644
index 7da05b9..0000000
--- a/uhd/PLIST
+++ /dev/null
@@ -1,3998 +0,0 @@
-@comment $NetBSD: PLIST,v 1.5 2014/10/04 12:40:17 makoto Exp $
-bin/nirio_programmer
-bin/uhd_cal_rx_iq_balance
-bin/uhd_cal_tx_dc_offset
-bin/uhd_cal_tx_iq_balance
-bin/uhd_find_devices
-bin/uhd_usrp_probe
-bin/usrp_n2xx_simple_net_burner
-bin/usrp_x3xx_fpga_burner
-include/uhd/config.hpp
-include/uhd/convert.hpp
-include/uhd/deprecated.hpp
-include/uhd/device.hpp
-include/uhd/device_deprecated.ipp
-include/uhd/exception.hpp
-include/uhd/property_tree.hpp
-include/uhd/property_tree.ipp
-include/uhd/stream.hpp
-include/uhd/transport/bounded_buffer.hpp
-include/uhd/transport/bounded_buffer.ipp
-include/uhd/transport/buffer_pool.hpp
-include/uhd/transport/if_addrs.hpp
-include/uhd/transport/tcp_zero_copy.hpp
-include/uhd/transport/udp_constants.hpp
-include/uhd/transport/udp_simple.hpp
-include/uhd/transport/udp_zero_copy.hpp
-include/uhd/transport/usb_control.hpp
-include/uhd/transport/usb_device_handle.hpp
-include/uhd/transport/usb_zero_copy.hpp
-include/uhd/transport/vrt_if_packet.hpp
-include/uhd/transport/zero_copy.hpp
-include/uhd/types/clock_config.hpp
-include/uhd/types/device_addr.hpp
-include/uhd/types/dict.hpp
-include/uhd/types/dict.ipp
-include/uhd/types/io_type.hpp
-include/uhd/types/mac_addr.hpp
-include/uhd/types/metadata.hpp
-include/uhd/types/otw_type.hpp
-include/uhd/types/ranges.hpp
-include/uhd/types/ref_vector.hpp
-include/uhd/types/sensors.hpp
-include/uhd/types/serial.hpp
-include/uhd/types/stream_cmd.hpp
-include/uhd/types/time_spec.hpp
-include/uhd/types/tune_request.hpp
-include/uhd/types/tune_result.hpp
-include/uhd/types/wb_iface.hpp
-include/uhd/usrp/dboard_base.hpp
-include/uhd/usrp/dboard_eeprom.hpp
-include/uhd/usrp/dboard_id.hpp
-include/uhd/usrp/dboard_iface.hpp
-include/uhd/usrp/dboard_manager.hpp
-include/uhd/usrp/gps_ctrl.hpp
-include/uhd/usrp/mboard_eeprom.hpp
-include/uhd/usrp/multi_usrp.hpp
-include/uhd/usrp/subdev_spec.hpp
-include/uhd/utils/algorithm.hpp
-include/uhd/utils/assert_has.hpp
-include/uhd/utils/assert_has.ipp
-include/uhd/utils/atomic.hpp
-include/uhd/utils/byteswap.hpp
-include/uhd/utils/byteswap.ipp
-include/uhd/utils/cast.hpp
-include/uhd/utils/csv.hpp
-include/uhd/utils/gain_group.hpp
-include/uhd/utils/images.hpp
-include/uhd/utils/log.hpp
-include/uhd/utils/msg.hpp
-include/uhd/utils/msg_task.hpp
-include/uhd/utils/paths.hpp
-include/uhd/utils/pimpl.hpp
-include/uhd/utils/platform.hpp
-include/uhd/utils/safe_call.hpp
-include/uhd/utils/safe_main.hpp
-include/uhd/utils/static.hpp
-include/uhd/utils/tasks.hpp
-include/uhd/utils/thread_priority.hpp
-include/uhd/version.hpp
-lib/libuhd.so
-lib/libuhd.so.003
-lib/libuhd.so.003.007
-lib/pkgconfig/uhd.pc
-lib/uhd/examples/benchmark_rate
-lib/uhd/examples/fpgpio
-lib/uhd/examples/latency_test
-lib/uhd/examples/network_relay
-lib/uhd/examples/rx_ascii_art_dft
-lib/uhd/examples/rx_multi_samples
-lib/uhd/examples/rx_samples_to_file
-lib/uhd/examples/rx_samples_to_udp
-lib/uhd/examples/rx_timed_samples
-lib/uhd/examples/test_dboard_coercion
-lib/uhd/examples/test_messages
-lib/uhd/examples/test_pps_input
-lib/uhd/examples/test_timed_commands
-lib/uhd/examples/transport_hammer
-lib/uhd/examples/tx_bursts
-lib/uhd/examples/tx_samples_from_file
-lib/uhd/examples/tx_timed_samples
-lib/uhd/examples/tx_waveforms
-lib/uhd/examples/txrx_loopback_to_file
-lib/uhd/tests/addr_test
-lib/uhd/tests/buffer_test
-lib/uhd/tests/byteswap_test
-lib/uhd/tests/cast_test
-lib/uhd/tests/convert_test
-lib/uhd/tests/dict_test
-lib/uhd/tests/error_test
-lib/uhd/tests/gain_group_test
-lib/uhd/tests/msg_test
-lib/uhd/tests/property_test
-lib/uhd/tests/ranges_test
-lib/uhd/tests/sph_recv_test
-lib/uhd/tests/sph_send_test
-lib/uhd/tests/subdev_spec_test
-lib/uhd/tests/time_spec_test
-lib/uhd/tests/vrt_test
-lib/uhd/utils/b2xx_fx3_utils
-lib/uhd/utils/fx2_init_eeprom
-lib/uhd/utils/query_gpsdo_sensors
-lib/uhd/utils/uhd_images_downloader.py
-lib/uhd/utils/usrp2_card_burner.py
-lib/uhd/utils/usrp2_card_burner_gui.py
-lib/uhd/utils/usrp_burn_db_eeprom
-lib/uhd/utils/usrp_burn_mb_eeprom
-lib/uhd/utils/usrp_n2xx_net_burner.py
-lib/uhd/utils/usrp_n2xx_net_burner_gui.py
-lib/uhd/utils/usrp_n2xx_simple_net_burner
-lib/uhd/utils/usrp_x3xx_fpga_burner
-man/man1/uhd_cal_rx_iq_balance.1
-man/man1/uhd_cal_tx_dc_offset.1
-man/man1/uhd_cal_tx_iq_balance.1
-man/man1/uhd_find_devices.1
-man/man1/uhd_images_downloader.1
-man/man1/uhd_usrp_probe.1
-man/man1/usrp2_card_burner.1
-man/man1/usrp_n2xx_simple_net_burner.1
-man/man1/usrp_x3xx_fpga_burner.1
-share/doc/uhd/LICENSE
-share/doc/uhd/README.md
-share/uhd/firmware/README.md
-share/uhd/firmware/fx2/.gitignore
-share/uhd/firmware/fx2/CMakeLists.txt
-share/uhd/firmware/fx2/b100/.gitignore
-share/uhd/firmware/fx2/b100/CMakeLists.txt
-share/uhd/firmware/fx2/b100/board_specific.c
-share/uhd/firmware/fx2/b100/eeprom_io.c
-share/uhd/firmware/fx2/b100/eeprom_io.h
-share/uhd/firmware/fx2/b100/fpga_load.c
-share/uhd/firmware/fx2/b100/fpga_rev2.c
-share/uhd/firmware/fx2/b100/fpga_rev2.h
-share/uhd/firmware/fx2/b100/gpif.c
-share/uhd/firmware/fx2/b100/usb_descriptors.a51
-share/uhd/firmware/fx2/b100/usrp_common.c
-share/uhd/firmware/fx2/b100/usrp_main.c
-share/uhd/firmware/fx2/b100/usrp_regs.h
-share/uhd/firmware/fx2/common/.gitignore
-share/uhd/firmware/fx2/common/_startup.a51
-share/uhd/firmware/fx2/common/_startup.a51.brittle
-share/uhd/firmware/fx2/common/delay.c
-share/uhd/firmware/fx2/common/delay.h
-share/uhd/firmware/fx2/common/eeprom_boot.a51
-share/uhd/firmware/fx2/common/eeprom_init.c
-share/uhd/firmware/fx2/common/fpga.h
-share/uhd/firmware/fx2/common/fpga_load.h
-share/uhd/firmware/fx2/common/fpga_regs0.h
-share/uhd/firmware/fx2/common/fpga_regs_common.h
-share/uhd/firmware/fx2/common/fpga_regs_common.v
-share/uhd/firmware/fx2/common/fpga_regs_standard.h
-share/uhd/firmware/fx2/common/fpga_regs_standard.v
-share/uhd/firmware/fx2/common/fx2regs.h
-share/uhd/firmware/fx2/common/fx2utils.c
-share/uhd/firmware/fx2/common/fx2utils.h
-share/uhd/firmware/fx2/common/i2c.c
-share/uhd/firmware/fx2/common/i2c.h
-share/uhd/firmware/fx2/common/init_gpif.c
-share/uhd/firmware/fx2/common/isr.c
-share/uhd/firmware/fx2/common/isr.h
-share/uhd/firmware/fx2/common/spi.c
-share/uhd/firmware/fx2/common/spi.h
-share/uhd/firmware/fx2/common/syncdelay.h
-share/uhd/firmware/fx2/common/timer.c
-share/uhd/firmware/fx2/common/timer.h
-share/uhd/firmware/fx2/common/usb_common.c
-share/uhd/firmware/fx2/common/usb_common.h
-share/uhd/firmware/fx2/common/usb_descriptors.h
-share/uhd/firmware/fx2/common/usb_requests.h
-share/uhd/firmware/fx2/common/usrp_commands.h
-share/uhd/firmware/fx2/common/usrp_common.h
-share/uhd/firmware/fx2/common/usrp_config.h
-share/uhd/firmware/fx2/common/usrp_globals.h
-share/uhd/firmware/fx2/common/usrp_i2c_addr.h
-share/uhd/firmware/fx2/common/usrp_ids.h
-share/uhd/firmware/fx2/common/usrp_interfaces.h
-share/uhd/firmware/fx2/common/usrp_spi_defs.h
-share/uhd/firmware/fx2/common/vectors.a51
-share/uhd/firmware/fx2/config/CMakeASM_SDCCInformation.cmake
-share/uhd/firmware/fx2/config/CMakeDetermineASM_SDCCCompiler.cmake
-share/uhd/firmware/fx2/config/CMakeTestASM_SDCCCompiler.cmake
-share/uhd/firmware/fx2/config/Rename.cmake
-share/uhd/firmware/fx2/config/Toolchain-sdcc.cmake
-share/uhd/firmware/fx2/usrp1/CMakeLists.txt
-share/uhd/firmware/fx2/usrp1/board_specific.c
-share/uhd/firmware/fx2/usrp1/eeprom_io.c
-share/uhd/firmware/fx2/usrp1/eeprom_io.h
-share/uhd/firmware/fx2/usrp1/fpga_load.c
-share/uhd/firmware/fx2/usrp1/fpga_rev2.c
-share/uhd/firmware/fx2/usrp1/fpga_rev2.h
-share/uhd/firmware/fx2/usrp1/gpif.c
-share/uhd/firmware/fx2/usrp1/gpif.gpf
-share/uhd/firmware/fx2/usrp1/usb_descriptors.a51
-share/uhd/firmware/fx2/usrp1/usrp_common.c
-share/uhd/firmware/fx2/usrp1/usrp_gpif.c
-share/uhd/firmware/fx2/usrp1/usrp_gpif_inline.h
-share/uhd/firmware/fx2/usrp1/usrp_main.c
-share/uhd/firmware/fx2/usrp1/usrp_regs.h
-share/uhd/firmware/fx2/utils/build_eeprom.py
-share/uhd/firmware/fx2/utils/edit-gpif-b100.py
-share/uhd/firmware/fx2/utils/edit-gpif.py
-share/uhd/firmware/fx2/utils/generate_regs.py
-share/uhd/firmware/fx3/README.md
-share/uhd/firmware/fx3/ad9361/include/ad9361_dispatch.h
-share/uhd/firmware/fx3/ad9361/include/ad9361_transaction.h
-share/uhd/firmware/fx3/ad9361/lib/ad9361_filter_taps.h
-share/uhd/firmware/fx3/ad9361/lib/ad9361_gain_tables.h
-share/uhd/firmware/fx3/ad9361/lib/ad9361_impl.c
-share/uhd/firmware/fx3/ad9361/lib/ad9361_synth_lut.h
-share/uhd/firmware/fx3/b200/.gitignore
-share/uhd/firmware/fx3/b200/b200_ad9361.c
-share/uhd/firmware/fx3/b200/b200_gpifconfig.h
-share/uhd/firmware/fx3/b200/b200_i2c.c
-share/uhd/firmware/fx3/b200/b200_i2c.h
-share/uhd/firmware/fx3/b200/b200_main.c
-share/uhd/firmware/fx3/b200/b200_main.h
-share/uhd/firmware/fx3/b200/b200_usb_descriptors.c
-share/uhd/firmware/fx3/b200/b200_vrq.h
-share/uhd/firmware/fx3/b200/fx3_mem_map.patch
-share/uhd/firmware/fx3/b200/makefile
-share/uhd/firmware/fx3/gpif2_designer/b200_v2.cydsn/b200_v2.cyfx
-share/uhd/firmware/fx3/gpif2_designer/b200_v2.cydsn/cyfxgpif2config.h
-share/uhd/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2model.xml
-share/uhd/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2timingsimulation.xml
-share/uhd/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2view.xml
-share/uhd/firmware/octoclock/Makefile
-share/uhd/firmware/octoclock/OctoClock.c
-share/uhd/firmware/x300/.gitignore
-share/uhd/firmware/x300/CMakeLists.txt
-share/uhd/firmware/x300/bin_to_coe.py
-share/uhd/firmware/x300/include/chinch.h
-share/uhd/firmware/x300/include/ethernet.h
-share/uhd/firmware/x300/include/ethertype.h
-share/uhd/firmware/x300/include/if_arp.h
-share/uhd/firmware/x300/include/link_state_route_proto.h
-share/uhd/firmware/x300/include/mdelay.h
-share/uhd/firmware/x300/include/print_addrs.h
-share/uhd/firmware/x300/include/printf.h
-share/uhd/firmware/x300/include/stdint.h
-share/uhd/firmware/x300/include/u3_net_stack.h
-share/uhd/firmware/x300/include/udp_uart.h
-share/uhd/firmware/x300/include/wb_i2c.h
-share/uhd/firmware/x300/include/wb_pkt_iface64.h
-share/uhd/firmware/x300/include/wb_uart.h
-share/uhd/firmware/x300/include/wb_utils.h
-share/uhd/firmware/x300/include/xge_mac.h
-share/uhd/firmware/x300/include/xge_phy.h
-share/uhd/firmware/x300/lib/CMakeLists.txt
-share/uhd/firmware/x300/lib/chinch.c
-share/uhd/firmware/x300/lib/ethernet.c
-share/uhd/firmware/x300/lib/link_state_route_proto.c
-share/uhd/firmware/x300/lib/mdelay.c
-share/uhd/firmware/x300/lib/print_addrs.c
-share/uhd/firmware/x300/lib/printf.c
-share/uhd/firmware/x300/lib/u3_net_stack.c
-share/uhd/firmware/x300/lib/udp_uart.c
-share/uhd/firmware/x300/lib/wb_i2c.c
-share/uhd/firmware/x300/lib/wb_pkt_iface64.c
-share/uhd/firmware/x300/lib/wb_uart.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/CHANGELOG
-share/uhd/firmware/x300/lwip/lwip-1.3.1/COPYING
-share/uhd/firmware/x300/lwip/lwip-1.3.1/FILES
-share/uhd/firmware/x300/lwip/lwip-1.3.1/README
-share/uhd/firmware/x300/lwip/lwip-1.3.1/doc/FILES
-share/uhd/firmware/x300/lwip/lwip-1.3.1/doc/contrib.txt
-share/uhd/firmware/x300/lwip/lwip-1.3.1/doc/rawapi.txt
-share/uhd/firmware/x300/lwip/lwip-1.3.1/doc/savannah.txt
-share/uhd/firmware/x300/lwip/lwip-1.3.1/doc/snmp_agent.txt
-share/uhd/firmware/x300/lwip/lwip-1.3.1/doc/sys_arch.txt
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/.hgignore
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/FILES
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/api_lib.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/api_msg.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/err.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/netbuf.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/netdb.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/netifapi.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/sockets.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/api/tcpip.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/dhcp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/dns.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/init.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/autoip.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/icmp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/igmp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/inet.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/inet_chksum.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/ip.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/ip_addr.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv4/ip_frag.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv6/README
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv6/icmp6.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv6/inet6.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv6/ip6.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/ipv6/ip6_addr.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/mem.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/memp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/netif.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/pbuf.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/raw.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/snmp/asn1_dec.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/snmp/asn1_enc.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/snmp/mib2.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/snmp/mib_structs.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/snmp/msg_in.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/snmp/msg_out.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/stats.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/sys.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/tcp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/tcp_in.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/tcp_out.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/core/udp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/autoip.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/icmp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/igmp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet_chksum.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_addr.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_frag.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv6/lwip/icmp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv6/lwip/inet.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip_addr.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/api.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/api_msg.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/arch.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/debug.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/def.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/dhcp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/dns.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/err.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/init.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/mem.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/memp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/memp_std.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/netbuf.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/netdb.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/netif.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/netifapi.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/opt.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/pbuf.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/raw.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/sio.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/snmp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/snmp_asn1.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/snmp_msg.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/snmp_structs.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/sockets.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/stats.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/sys.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/tcp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/tcpip.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/lwip/udp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/netif/etharp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/netif/loopif.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/include/netif/slipif.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/FILES
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/etharp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ethernetif.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/loopif.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/auth.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/auth.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/chap.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/chap.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/chpms.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/chpms.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/fsm.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/fsm.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/lcp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/lcp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/magic.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/magic.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/md5.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/md5.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/pap.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/pap.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/ppp.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/ppp.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/pppdebug.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/randm.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/randm.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/vj.c
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/vj.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/ppp/vjbsdhdr.h
-share/uhd/firmware/x300/lwip/lwip-1.3.1/src/netif/slipif.c
-share/uhd/firmware/x300/lwip/lwipopts.h
-share/uhd/firmware/x300/lwip/lwippools.h
-share/uhd/firmware/x300/lwip_port/arch/cc.h
-share/uhd/firmware/x300/lwip_port/arch/perf.h
-share/uhd/firmware/x300/lwip_port/netif/eth_driver.c
-share/uhd/firmware/x300/lwip_port/netif/eth_driver.h
-share/uhd/firmware/x300/x300/CMakeLists.txt
-share/uhd/firmware/x300/x300/x300_defs.h
-share/uhd/firmware/x300/x300/x300_init.c
-share/uhd/firmware/x300/x300/x300_init.h
-share/uhd/firmware/x300/x300/x300_main.c
-share/uhd/firmware/zpu/.gitignore
-share/uhd/firmware/zpu/CMakeLists.txt
-share/uhd/firmware/zpu/apps/txrx_uhd.c
-share/uhd/firmware/zpu/bin/bin_to_mif.py
-share/uhd/firmware/zpu/bin/bin_to_ram_macro_init.py
-share/uhd/firmware/zpu/bin/divisors.py
-share/uhd/firmware/zpu/bin/elf_to_sbf
-share/uhd/firmware/zpu/bin/sbf.py
-share/uhd/firmware/zpu/bin/serial_loader
-share/uhd/firmware/zpu/bin/uart_ihex_flash_loader.py
-share/uhd/firmware/zpu/bin/uart_ihex_ram_loader.py
-share/uhd/firmware/zpu/lib/CMakeLists.txt
-share/uhd/firmware/zpu/lib/_exit.c
-share/uhd/firmware/zpu/lib/abort.c
-share/uhd/firmware/zpu/lib/ad9510.c
-share/uhd/firmware/zpu/lib/ad9510.h
-share/uhd/firmware/zpu/lib/arp_cache.c
-share/uhd/firmware/zpu/lib/arp_cache.h
-share/uhd/firmware/zpu/lib/banal.c
-share/uhd/firmware/zpu/lib/banal.h
-share/uhd/firmware/zpu/lib/clocks.c
-share/uhd/firmware/zpu/lib/clocks.h
-share/uhd/firmware/zpu/lib/compiler.h
-share/uhd/firmware/zpu/lib/eeprom.c
-share/uhd/firmware/zpu/lib/eth_addrs.c
-share/uhd/firmware/zpu/lib/eth_mac.c
-share/uhd/firmware/zpu/lib/eth_mac.h
-share/uhd/firmware/zpu/lib/ethernet.h
-share/uhd/firmware/zpu/lib/ethertype.h
-share/uhd/firmware/zpu/lib/exit.c
-share/uhd/firmware/zpu/lib/hal_io.c
-share/uhd/firmware/zpu/lib/hal_io.h
-share/uhd/firmware/zpu/lib/hal_uart.c
-share/uhd/firmware/zpu/lib/hal_uart.h
-share/uhd/firmware/zpu/lib/i2c.c
-share/uhd/firmware/zpu/lib/i2c.h
-share/uhd/firmware/zpu/lib/i2c_async.c
-share/uhd/firmware/zpu/lib/i2c_async.h
-share/uhd/firmware/zpu/lib/if_arp.h
-share/uhd/firmware/zpu/lib/ihex.c
-share/uhd/firmware/zpu/lib/ihex.h
-share/uhd/firmware/zpu/lib/mdelay.c
-share/uhd/firmware/zpu/lib/mdelay.h
-share/uhd/firmware/zpu/lib/memcpy_wa.c
-share/uhd/firmware/zpu/lib/memcpy_wa.h
-share/uhd/firmware/zpu/lib/memory_map.h
-share/uhd/firmware/zpu/lib/memset_wa.c
-share/uhd/firmware/zpu/lib/memset_wa.h
-share/uhd/firmware/zpu/lib/net/eth_mac_addr.h
-share/uhd/firmware/zpu/lib/net/padded_eth_hdr.h
-share/uhd/firmware/zpu/lib/net/socket_address.h
-share/uhd/firmware/zpu/lib/net_common.c
-share/uhd/firmware/zpu/lib/net_common.h
-share/uhd/firmware/zpu/lib/nonstdio.c
-share/uhd/firmware/zpu/lib/nonstdio.h
-share/uhd/firmware/zpu/lib/pic.c
-share/uhd/firmware/zpu/lib/pic.h
-share/uhd/firmware/zpu/lib/pkt_ctrl.c
-share/uhd/firmware/zpu/lib/pkt_ctrl.h
-share/uhd/firmware/zpu/lib/print_addrs.c
-share/uhd/firmware/zpu/lib/print_buffer.c
-share/uhd/firmware/zpu/lib/print_rmon_regs.c
-share/uhd/firmware/zpu/lib/print_rmon_regs.h
-share/uhd/firmware/zpu/lib/printf.c
-share/uhd/firmware/zpu/lib/printf.c.smaller
-share/uhd/firmware/zpu/lib/spi.c
-share/uhd/firmware/zpu/lib/spi.h
-share/uhd/firmware/zpu/lib/stdint.h
-share/uhd/firmware/zpu/lib/stdio.h
-share/uhd/firmware/zpu/lib/u2_init.c
-share/uhd/firmware/zpu/lib/u2_init.h
-share/uhd/firmware/zpu/lib/udp_fw_update.h
-share/uhd/firmware/zpu/lib/udp_uart.c
-share/uhd/firmware/zpu/lib/udp_uart.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/CHANGELOG
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/COPYING
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/FILES
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/README
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/doc/FILES
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/doc/contrib.txt
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/doc/rawapi.txt
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/doc/savannah.txt
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/doc/snmp_agent.txt
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/doc/sys_arch.txt
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/.hgignore
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/FILES
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/api_lib.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/api_msg.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/err.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/netbuf.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/netdb.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/netifapi.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/sockets.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/api/tcpip.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/dhcp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/dns.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/init.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/autoip.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/icmp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/igmp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/inet.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/inet_chksum.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip_addr.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip_frag.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/README
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/icmp6.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/inet6.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/ip6.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/ip6_addr.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/mem.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/memp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/netif.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/pbuf.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/raw.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_dec.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_enc.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib2.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib_structs.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_in.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_out.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/stats.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/sys.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp_in.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp_out.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/core/udp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/autoip.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/icmp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/igmp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet_chksum.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_addr.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_frag.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/icmp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/inet.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip_addr.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/api.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/api_msg.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/arch.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/debug.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/def.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/dhcp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/dns.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/err.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/init.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/mem.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/memp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/memp_std.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netbuf.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netdb.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netif.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netifapi.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/opt.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/pbuf.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/raw.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sio.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_asn1.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_msg.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_structs.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sockets.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/stats.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sys.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/tcp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/tcpip.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/udp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/etharp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/loopif.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/slipif.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/FILES
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/etharp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ethernetif.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/loopif.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pppdebug.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.c
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vjbsdhdr.h
-share/uhd/firmware/zpu/lwip/lwip-1.3.1/src/netif/slipif.c
-share/uhd/firmware/zpu/lwip/lwipopts.h
-share/uhd/firmware/zpu/lwip/lwippools.h
-share/uhd/firmware/zpu/lwip_port/arch/cc.h
-share/uhd/firmware/zpu/lwip_port/arch/perf.h
-share/uhd/firmware/zpu/lwip_port/netif/eth_driver.c
-share/uhd/firmware/zpu/lwip_port/netif/eth_driver.h
-share/uhd/firmware/zpu/usrp2/CMakeLists.txt
-share/uhd/firmware/zpu/usrp2/eth_phy.h
-share/uhd/firmware/zpu/usrp2/ethernet.c
-share/uhd/firmware/zpu/usrp2/sd.c
-share/uhd/firmware/zpu/usrp2/sd.h
-share/uhd/firmware/zpu/usrp2p/CMakeLists.txt
-share/uhd/firmware/zpu/usrp2p/bootconfig.h
-share/uhd/firmware/zpu/usrp2p/bootloader/CMakeLists.txt
-share/uhd/firmware/zpu/usrp2p/bootloader_utils.c
-share/uhd/firmware/zpu/usrp2p/bootloader_utils.h
-share/uhd/firmware/zpu/usrp2p/eth_phy.h
-share/uhd/firmware/zpu/usrp2p/ethernet.c
-share/uhd/firmware/zpu/usrp2p/spi_flash.c
-share/uhd/firmware/zpu/usrp2p/spi_flash.h
-share/uhd/firmware/zpu/usrp2p/spi_flash_private.h
-share/uhd/firmware/zpu/usrp2p/spi_flash_read.c
-share/uhd/firmware/zpu/usrp2p/spif.c
-share/uhd/firmware/zpu/usrp2p/u2p_init.c
-share/uhd/firmware/zpu/usrp2p/u2p_init.h
-share/uhd/firmware/zpu/usrp2p/udp_fw_update.c
-share/uhd/firmware/zpu/usrp2p/xilinx_s3_icap.c
-share/uhd/firmware/zpu/usrp2p/xilinx_s3_icap.h
-share/uhd/fpga/README.txt
-share/uhd/fpga/usrp1/Makefile.am
-share/uhd/fpga/usrp1/Makefile.extra
-share/uhd/fpga/usrp1/TODO
-share/uhd/fpga/usrp1/common/fpga_regs_common.v
-share/uhd/fpga/usrp1/common/fpga_regs_standard.v
-share/uhd/fpga/usrp1/gen_makefile_extra.py
-share/uhd/fpga/usrp1/inband_lib/chan_fifo_reader.v
-share/uhd/fpga/usrp1/inband_lib/channel_demux.v
-share/uhd/fpga/usrp1/inband_lib/channel_ram.v
-share/uhd/fpga/usrp1/inband_lib/cmd_reader.v
-share/uhd/fpga/usrp1/inband_lib/packet_builder.v
-share/uhd/fpga/usrp1/inband_lib/register_io.v
-share/uhd/fpga/usrp1/inband_lib/rx_buffer_inband.v
-share/uhd/fpga/usrp1/inband_lib/tx_buffer_inband.v
-share/uhd/fpga/usrp1/inband_lib/tx_packer.v
-share/uhd/fpga/usrp1/inband_lib/usb_packet_fifo.v
-share/uhd/fpga/usrp1/megacells/.gitignore
-share/uhd/fpga/usrp1/megacells/accum32.bsf
-share/uhd/fpga/usrp1/megacells/accum32.cmp
-share/uhd/fpga/usrp1/megacells/accum32.inc
-share/uhd/fpga/usrp1/megacells/accum32.v
-share/uhd/fpga/usrp1/megacells/accum32_bb.v
-share/uhd/fpga/usrp1/megacells/accum32_inst.v
-share/uhd/fpga/usrp1/megacells/add32.bsf
-share/uhd/fpga/usrp1/megacells/add32.cmp
-share/uhd/fpga/usrp1/megacells/add32.inc
-share/uhd/fpga/usrp1/megacells/add32.v
-share/uhd/fpga/usrp1/megacells/add32_bb.v
-share/uhd/fpga/usrp1/megacells/add32_inst.v
-share/uhd/fpga/usrp1/megacells/addsub16.bsf
-share/uhd/fpga/usrp1/megacells/addsub16.cmp
-share/uhd/fpga/usrp1/megacells/addsub16.inc
-share/uhd/fpga/usrp1/megacells/addsub16.v
-share/uhd/fpga/usrp1/megacells/addsub16_bb.v
-share/uhd/fpga/usrp1/megacells/addsub16_inst.v
-share/uhd/fpga/usrp1/megacells/bustri.bsf
-share/uhd/fpga/usrp1/megacells/bustri.cmp
-share/uhd/fpga/usrp1/megacells/bustri.inc
-share/uhd/fpga/usrp1/megacells/bustri.v
-share/uhd/fpga/usrp1/megacells/bustri_bb.v
-share/uhd/fpga/usrp1/megacells/bustri_inst.v
-share/uhd/fpga/usrp1/megacells/clk_doubler.v
-share/uhd/fpga/usrp1/megacells/clk_doubler_bb.v
-share/uhd/fpga/usrp1/megacells/dspclkpll.v
-share/uhd/fpga/usrp1/megacells/dspclkpll_bb.v
-share/uhd/fpga/usrp1/megacells/fifo_1kx16.bsf
-share/uhd/fpga/usrp1/megacells/fifo_1kx16.cmp
-share/uhd/fpga/usrp1/megacells/fifo_1kx16.inc
-share/uhd/fpga/usrp1/megacells/fifo_1kx16.v
-share/uhd/fpga/usrp1/megacells/fifo_1kx16_bb.v
-share/uhd/fpga/usrp1/megacells/fifo_1kx16_inst.v
-share/uhd/fpga/usrp1/megacells/fifo_2k.v
-share/uhd/fpga/usrp1/megacells/fifo_2k_bb.v
-share/uhd/fpga/usrp1/megacells/fifo_4k.v
-share/uhd/fpga/usrp1/megacells/fifo_4k_18.v
-share/uhd/fpga/usrp1/megacells/fifo_4k_bb.v
-share/uhd/fpga/usrp1/megacells/fifo_4kx16_dc.bsf
-share/uhd/fpga/usrp1/megacells/fifo_4kx16_dc.cmp
-share/uhd/fpga/usrp1/megacells/fifo_4kx16_dc.inc
-share/uhd/fpga/usrp1/megacells/fifo_4kx16_dc.v
-share/uhd/fpga/usrp1/megacells/fifo_4kx16_dc_bb.v
-share/uhd/fpga/usrp1/megacells/fifo_4kx16_dc_inst.v
-share/uhd/fpga/usrp1/megacells/mylpm_addsub.bsf
-share/uhd/fpga/usrp1/megacells/mylpm_addsub.cmp
-share/uhd/fpga/usrp1/megacells/mylpm_addsub.inc
-share/uhd/fpga/usrp1/megacells/mylpm_addsub.v
-share/uhd/fpga/usrp1/megacells/mylpm_addsub_bb.v
-share/uhd/fpga/usrp1/megacells/mylpm_addsub_inst.v
-share/uhd/fpga/usrp1/megacells/pll.v
-share/uhd/fpga/usrp1/megacells/pll_bb.v
-share/uhd/fpga/usrp1/megacells/pll_inst.v
-share/uhd/fpga/usrp1/megacells/sub32.bsf
-share/uhd/fpga/usrp1/megacells/sub32.cmp
-share/uhd/fpga/usrp1/megacells/sub32.inc
-share/uhd/fpga/usrp1/megacells/sub32.v
-share/uhd/fpga/usrp1/megacells/sub32_bb.v
-share/uhd/fpga/usrp1/megacells/sub32_inst.v
-share/uhd/fpga/usrp1/models/bustri.v
-share/uhd/fpga/usrp1/models/fifo.v
-share/uhd/fpga/usrp1/models/fifo_1c_1k.v
-share/uhd/fpga/usrp1/models/fifo_1c_2k.v
-share/uhd/fpga/usrp1/models/fifo_1c_4k.v
-share/uhd/fpga/usrp1/models/fifo_1k.v
-share/uhd/fpga/usrp1/models/fifo_2k.v
-share/uhd/fpga/usrp1/models/fifo_4k.v
-share/uhd/fpga/usrp1/models/fifo_4k_18.v
-share/uhd/fpga/usrp1/models/pll.v
-share/uhd/fpga/usrp1/models/ssram.v
-share/uhd/fpga/usrp1/rbf/.gitignore
-share/uhd/fpga/usrp1/rbf/Makefile.am
-share/uhd/fpga/usrp1/rbf/rev2/.gitignore
-share/uhd/fpga/usrp1/rbf/rev2/Makefile.am
-share/uhd/fpga/usrp1/rbf/rev2/inband_1rxhb_1tx.rbf
-share/uhd/fpga/usrp1/rbf/rev2/inband_2rxhb_2tx.rbf
-share/uhd/fpga/usrp1/rbf/rev2/multi_2rxhb_2tx.rbf
-share/uhd/fpga/usrp1/rbf/rev2/multi_4rx_0tx.rbf
-share/uhd/fpga/usrp1/rbf/rev2/std_2rxhb_2tx.rbf
-share/uhd/fpga/usrp1/rbf/rev2/std_4rx_0tx.rbf
-share/uhd/fpga/usrp1/rbf/rev4/.gitignore
-share/uhd/fpga/usrp1/rbf/rev4/Makefile.am
-share/uhd/fpga/usrp1/rbf/rev4/inband_1rxhb_1tx.rbf
-share/uhd/fpga/usrp1/rbf/rev4/inband_2rxhb_2tx.rbf
-share/uhd/fpga/usrp1/rbf/rev4/multi_2rxhb_2tx.rbf
-share/uhd/fpga/usrp1/rbf/rev4/multi_4rx_0tx.rbf
-share/uhd/fpga/usrp1/rbf/rev4/std_2rxhb_2tx.rbf
-share/uhd/fpga/usrp1/rbf/rev4/std_4rx_0tx.rbf
-share/uhd/fpga/usrp1/sdr_lib/.gitignore
-share/uhd/fpga/usrp1/sdr_lib/adc_interface.v
-share/uhd/fpga/usrp1/sdr_lib/atr_delay.v
-share/uhd/fpga/usrp1/sdr_lib/bidir_reg.v
-share/uhd/fpga/usrp1/sdr_lib/cic_dec_shifter.v
-share/uhd/fpga/usrp1/sdr_lib/cic_decim.v
-share/uhd/fpga/usrp1/sdr_lib/cic_int_shifter.v
-share/uhd/fpga/usrp1/sdr_lib/cic_interp.v
-share/uhd/fpga/usrp1/sdr_lib/clk_divider.v
-share/uhd/fpga/usrp1/sdr_lib/cordic.v
-share/uhd/fpga/usrp1/sdr_lib/cordic_stage.v
-share/uhd/fpga/usrp1/sdr_lib/ddc.v
-share/uhd/fpga/usrp1/sdr_lib/dpram.v
-share/uhd/fpga/usrp1/sdr_lib/duc.v
-share/uhd/fpga/usrp1/sdr_lib/ext_fifo.v
-share/uhd/fpga/usrp1/sdr_lib/gen_cordic_consts.py
-share/uhd/fpga/usrp1/sdr_lib/gen_sync.v
-share/uhd/fpga/usrp1/sdr_lib/hb/acc.v
-share/uhd/fpga/usrp1/sdr_lib/hb/coeff_rom.v
-share/uhd/fpga/usrp1/sdr_lib/hb/halfband_decim.v
-share/uhd/fpga/usrp1/sdr_lib/hb/halfband_interp.v
-share/uhd/fpga/usrp1/sdr_lib/hb/hbd_tb/HBD
-share/uhd/fpga/usrp1/sdr_lib/hb/hbd_tb/really_golden
-share/uhd/fpga/usrp1/sdr_lib/hb/hbd_tb/regression
-share/uhd/fpga/usrp1/sdr_lib/hb/hbd_tb/run_hbd
-share/uhd/fpga/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v
-share/uhd/fpga/usrp1/sdr_lib/hb/mac.v
-share/uhd/fpga/usrp1/sdr_lib/hb/mult.v
-share/uhd/fpga/usrp1/sdr_lib/hb/ram16_2port.v
-share/uhd/fpga/usrp1/sdr_lib/hb/ram16_2sum.v
-share/uhd/fpga/usrp1/sdr_lib/hb/ram32_2sum.v
-share/uhd/fpga/usrp1/sdr_lib/io_pins.v
-share/uhd/fpga/usrp1/sdr_lib/master_control.v
-share/uhd/fpga/usrp1/sdr_lib/master_control_multi.v
-share/uhd/fpga/usrp1/sdr_lib/phase_acc.v
-share/uhd/fpga/usrp1/sdr_lib/ram.v
-share/uhd/fpga/usrp1/sdr_lib/ram16.v
-share/uhd/fpga/usrp1/sdr_lib/ram32.v
-share/uhd/fpga/usrp1/sdr_lib/ram64.v
-share/uhd/fpga/usrp1/sdr_lib/rssi.v
-share/uhd/fpga/usrp1/sdr_lib/rx_buffer.v
-share/uhd/fpga/usrp1/sdr_lib/rx_chain.v
-share/uhd/fpga/usrp1/sdr_lib/rx_chain_dual.v
-share/uhd/fpga/usrp1/sdr_lib/rx_dcoffset.v
-share/uhd/fpga/usrp1/sdr_lib/serial_io.v
-share/uhd/fpga/usrp1/sdr_lib/setting_reg.v
-share/uhd/fpga/usrp1/sdr_lib/setting_reg_masked.v
-share/uhd/fpga/usrp1/sdr_lib/sign_extend.v
-share/uhd/fpga/usrp1/sdr_lib/strobe_gen.v
-share/uhd/fpga/usrp1/sdr_lib/tx_buffer.v
-share/uhd/fpga/usrp1/sdr_lib/tx_chain.v
-share/uhd/fpga/usrp1/sdr_lib/tx_chain_hb.v
-share/uhd/fpga/usrp1/tb/.gitignore
-share/uhd/fpga/usrp1/tb/cbus_tb.v
-share/uhd/fpga/usrp1/tb/cordic_tb.v
-share/uhd/fpga/usrp1/tb/decim_tb.v
-share/uhd/fpga/usrp1/tb/fullchip_tb.v
-share/uhd/fpga/usrp1/tb/interp_tb.v
-share/uhd/fpga/usrp1/tb/justinterp_tb.v
-share/uhd/fpga/usrp1/tb/makesine.pl
-share/uhd/fpga/usrp1/tb/run_cordic
-share/uhd/fpga/usrp1/tb/run_fullchip
-share/uhd/fpga/usrp1/tb/usrp_tasks.v
-share/uhd/fpga/usrp1/toplevel/include/common_config_1rxhb_1tx.vh
-share/uhd/fpga/usrp1/toplevel/include/common_config_2rx_0tx.vh
-share/uhd/fpga/usrp1/toplevel/include/common_config_2rxhb_0tx.vh
-share/uhd/fpga/usrp1/toplevel/include/common_config_2rxhb_2tx.vh
-share/uhd/fpga/usrp1/toplevel/include/common_config_4rx_0tx.vh
-share/uhd/fpga/usrp1/toplevel/include/common_config_bottom.vh
-share/uhd/fpga/usrp1/toplevel/mrfm/.gitignore
-share/uhd/fpga/usrp1/toplevel/mrfm/biquad_2stage.v
-share/uhd/fpga/usrp1/toplevel/mrfm/biquad_6stage.v
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.csf
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.esf
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.psf
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.py
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.qpf
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.qsf
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.v
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm.vh
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm_compensator.v
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm_fft.py
-share/uhd/fpga/usrp1/toplevel/mrfm/mrfm_proc.v
-share/uhd/fpga/usrp1/toplevel/mrfm/shifter.v
-share/uhd/fpga/usrp1/toplevel/sizetest/.gitignore
-share/uhd/fpga/usrp1/toplevel/sizetest/sizetest.csf
-share/uhd/fpga/usrp1/toplevel/sizetest/sizetest.psf
-share/uhd/fpga/usrp1/toplevel/sizetest/sizetest.quartus
-share/uhd/fpga/usrp1/toplevel/sizetest/sizetest.ssf
-share/uhd/fpga/usrp1/toplevel/sizetest/sizetest.v
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/.gitignore
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/config.vh
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.csf
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.esf
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.psf
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qpf
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
-share/uhd/fpga/usrp1/toplevel/usrp_inband_usb/usrp_inband_usb.v
-share/uhd/fpga/usrp1/toplevel/usrp_multi/.gitignore
-share/uhd/fpga/usrp1/toplevel/usrp_multi/config.vh
-share/uhd/fpga/usrp1/toplevel/usrp_multi/usrp_multi.csf
-share/uhd/fpga/usrp1/toplevel/usrp_multi/usrp_multi.esf
-share/uhd/fpga/usrp1/toplevel/usrp_multi/usrp_multi.psf
-share/uhd/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qpf
-share/uhd/fpga/usrp1/toplevel/usrp_multi/usrp_multi.qsf
-share/uhd/fpga/usrp1/toplevel/usrp_multi/usrp_multi.v
-share/uhd/fpga/usrp1/toplevel/usrp_std/.gitignore
-share/uhd/fpga/usrp1/toplevel/usrp_std/config.vh
-share/uhd/fpga/usrp1/toplevel/usrp_std/usrp_std.csf
-share/uhd/fpga/usrp1/toplevel/usrp_std/usrp_std.esf
-share/uhd/fpga/usrp1/toplevel/usrp_std/usrp_std.psf
-share/uhd/fpga/usrp1/toplevel/usrp_std/usrp_std.qpf
-share/uhd/fpga/usrp1/toplevel/usrp_std/usrp_std.qsf
-share/uhd/fpga/usrp1/toplevel/usrp_std/usrp_std.v
-share/uhd/fpga/usrp2/boot_cpld/.gitignore
-share/uhd/fpga/usrp2/boot_cpld/_impact.cmd
-share/uhd/fpga/usrp2/boot_cpld/boot_cpld.ipf
-share/uhd/fpga/usrp2/boot_cpld/boot_cpld.ise
-share/uhd/fpga/usrp2/boot_cpld/boot_cpld.lfp
-share/uhd/fpga/usrp2/boot_cpld/boot_cpld.ucf
-share/uhd/fpga/usrp2/boot_cpld/boot_cpld.v
-share/uhd/fpga/usrp2/control_lib/.gitignore
-share/uhd/fpga/usrp2/control_lib/CRC16_D16.v
-share/uhd/fpga/usrp2/control_lib/Makefile.srcs
-share/uhd/fpga/usrp2/control_lib/atr_controller.v
-share/uhd/fpga/usrp2/control_lib/atr_controller16.v
-share/uhd/fpga/usrp2/control_lib/bin2gray.v
-share/uhd/fpga/usrp2/control_lib/bootram.v
-share/uhd/fpga/usrp2/control_lib/bootrom.mem
-share/uhd/fpga/usrp2/control_lib/clock_bootstrap_rom.v
-share/uhd/fpga/usrp2/control_lib/clock_control.v
-share/uhd/fpga/usrp2/control_lib/clock_control_tb.v
-share/uhd/fpga/usrp2/control_lib/cmdfile
-share/uhd/fpga/usrp2/control_lib/dbsm.v
-share/uhd/fpga/usrp2/control_lib/dcache.v
-share/uhd/fpga/usrp2/control_lib/decoder_3_8.v
-share/uhd/fpga/usrp2/control_lib/double_buffer.v
-share/uhd/fpga/usrp2/control_lib/double_buffer_tb.v
-share/uhd/fpga/usrp2/control_lib/dpram32.v
-share/uhd/fpga/usrp2/control_lib/fifo_to_wb.v
-share/uhd/fpga/usrp2/control_lib/fifo_to_wb_tb.v
-share/uhd/fpga/usrp2/control_lib/gpio_atr.v
-share/uhd/fpga/usrp2/control_lib/gray2bin.v
-share/uhd/fpga/usrp2/control_lib/gray_send.v
-share/uhd/fpga/usrp2/control_lib/icache.v
-share/uhd/fpga/usrp2/control_lib/longfifo.v
-share/uhd/fpga/usrp2/control_lib/medfifo.v
-share/uhd/fpga/usrp2/control_lib/mux4.v
-share/uhd/fpga/usrp2/control_lib/mux8.v
-share/uhd/fpga/usrp2/control_lib/mux_32_4.v
-share/uhd/fpga/usrp2/control_lib/nsgpio.v
-share/uhd/fpga/usrp2/control_lib/nsgpio16LE.v
-share/uhd/fpga/usrp2/control_lib/oneshot_2clk.v
-share/uhd/fpga/usrp2/control_lib/pic.v
-share/uhd/fpga/usrp2/control_lib/priority_enc.v
-share/uhd/fpga/usrp2/control_lib/quad_uart.v
-share/uhd/fpga/usrp2/control_lib/ram_2port.v
-share/uhd/fpga/usrp2/control_lib/ram_2port_mixed_width.v
-share/uhd/fpga/usrp2/control_lib/ram_harv_cache.v
-share/uhd/fpga/usrp2/control_lib/ram_harvard.v
-share/uhd/fpga/usrp2/control_lib/ram_harvard2.v
-share/uhd/fpga/usrp2/control_lib/ram_loader.v
-share/uhd/fpga/usrp2/control_lib/ram_wb_harvard.v
-share/uhd/fpga/usrp2/control_lib/reset_sync.v
-share/uhd/fpga/usrp2/control_lib/s3a_icap_wb.v
-share/uhd/fpga/usrp2/control_lib/sd_spi.v
-share/uhd/fpga/usrp2/control_lib/sd_spi_tb.v
-share/uhd/fpga/usrp2/control_lib/sd_spi_wb.v
-share/uhd/fpga/usrp2/control_lib/setting_reg.v
-share/uhd/fpga/usrp2/control_lib/settings_bus.v
-share/uhd/fpga/usrp2/control_lib/settings_bus_16LE.v
-share/uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v
-share/uhd/fpga/usrp2/control_lib/settings_fifo_ctrl.v
-share/uhd/fpga/usrp2/control_lib/shortfifo.v
-share/uhd/fpga/usrp2/control_lib/simple_i2c_core.v
-share/uhd/fpga/usrp2/control_lib/simple_spi_core.v
-share/uhd/fpga/usrp2/control_lib/simple_uart.v
-share/uhd/fpga/usrp2/control_lib/simple_uart_rx.v
-share/uhd/fpga/usrp2/control_lib/simple_uart_tx.v
-share/uhd/fpga/usrp2/control_lib/spi.v
-share/uhd/fpga/usrp2/control_lib/srl.v
-share/uhd/fpga/usrp2/control_lib/ss_rcvr.v
-share/uhd/fpga/usrp2/control_lib/system_control.v
-share/uhd/fpga/usrp2/control_lib/system_control_tb.v
-share/uhd/fpga/usrp2/control_lib/traffic_cop.v
-share/uhd/fpga/usrp2/control_lib/user_settings.v
-share/uhd/fpga/usrp2/control_lib/v5icap_wb.v
-share/uhd/fpga/usrp2/control_lib/wb_1master.v
-share/uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v
-share/uhd/fpga/usrp2/control_lib/wb_bus_writer.v
-share/uhd/fpga/usrp2/control_lib/wb_output_pins32.v
-share/uhd/fpga/usrp2/control_lib/wb_ram_block.v
-share/uhd/fpga/usrp2/control_lib/wb_ram_dist.v
-share/uhd/fpga/usrp2/control_lib/wb_readback_mux.v
-share/uhd/fpga/usrp2/control_lib/wb_readback_mux_16LE.v
-share/uhd/fpga/usrp2/control_lib/wb_regfile_2clock.v
-share/uhd/fpga/usrp2/control_lib/wb_semaphore.v
-share/uhd/fpga/usrp2/control_lib/wb_sim.v
-share/uhd/fpga/usrp2/coregen/.gitignore
-share/uhd/fpga/usrp2/coregen/Makefile.srcs
-share/uhd/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs
-share/uhd/fpga/usrp2/coregen/coregen.cgp
-share/uhd/fpga/usrp2/coregen/coregen_s6.cgc
-share/uhd/fpga/usrp2/coregen/coregen_s6.cgp
-share/uhd/fpga/usrp2/coregen/fifo_generator_release_notes.txt
-share/uhd/fpga/usrp2/coregen/fifo_generator_ug175.pdf
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.asy
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.gise
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk.xise
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_s6_1Kx36_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.asy
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.gise
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk.xise
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_s6_2Kx36_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk.asy
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk.gise
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk.xise
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_s6_512x36_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.gise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ncf
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.gise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ncf
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.xise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ncf
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt
-share/uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.asy
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.gise
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.ucf
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.v
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.veo
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.xco
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.xdc
-share/uhd/fpga/usrp2/coregen/pll_100_40_75.xise
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/clk_wiz_v3_5_readme.txt
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_gsg521.pdf
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_readme.txt
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.ucf
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.xdc
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/implement.bat
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/implement.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.bat
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_ise.tcl
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.bat
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/planAhead_rdn.tcl
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/xst.prj
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/implement/xst.scr
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simcmds.tcl
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.bat
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_isim.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.bat
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.do
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_mti.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_ncsim.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/simulate_vcs.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ucli_commands.key
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/vcs_session.tcl
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.do
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/wave.sv
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/pll_100_40_75_tb.v
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/pll_100_40_75_tb.v
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/sdf_cmd_file
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simcmds.tcl
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_isim.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.bat
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.do
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_mti.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_ncsim.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/simulate_vcs.sh
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ucli_commands.key
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/vcs_session.tcl
-share/uhd/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/wave.do
-share/uhd/fpga/usrp2/coregen/pll_100_40_75_exdes.ncf
-share/uhd/fpga/usrp2/coregen/pll_100_40_75_flist.txt
-share/uhd/fpga/usrp2/coregen/pll_100_40_75_xmdf.tcl
-share/uhd/fpga/usrp2/custom/custom_dsp_rx.v
-share/uhd/fpga/usrp2/custom/custom_dsp_tx.v
-share/uhd/fpga/usrp2/custom/custom_engine_rx.v
-share/uhd/fpga/usrp2/custom/custom_engine_tx.v
-share/uhd/fpga/usrp2/custom/power_trig.v
-share/uhd/fpga/usrp2/custom/power_trig_tb.v
-share/uhd/fpga/usrp2/extramfifo/.gitignore
-share/uhd/fpga/usrp2/extramfifo/Makefile.srcs
-share/uhd/fpga/usrp2/extramfifo/ext_fifo.v
-share/uhd/fpga/usrp2/extramfifo/ext_fifo_tb.cmd
-share/uhd/fpga/usrp2/extramfifo/ext_fifo_tb.prj
-share/uhd/fpga/usrp2/extramfifo/ext_fifo_tb.sav
-share/uhd/fpga/usrp2/extramfifo/ext_fifo_tb.sh
-share/uhd/fpga/usrp2/extramfifo/ext_fifo_tb.v
-share/uhd/fpga/usrp2/extramfifo/icon.v
-share/uhd/fpga/usrp2/extramfifo/icon.xco
-share/uhd/fpga/usrp2/extramfifo/ila.v
-share/uhd/fpga/usrp2/extramfifo/ila.xco
-share/uhd/fpga/usrp2/extramfifo/nobl_fifo.v
-share/uhd/fpga/usrp2/extramfifo/nobl_if.v
-share/uhd/fpga/usrp2/extramfifo/refill_randomizer.v
-share/uhd/fpga/usrp2/extramfifo/test_sram_if.v
-share/uhd/fpga/usrp2/fifo/.gitignore
-share/uhd/fpga/usrp2/fifo/Makefile.srcs
-share/uhd/fpga/usrp2/fifo/add_routing_header.v
-share/uhd/fpga/usrp2/fifo/buffer_int.v
-share/uhd/fpga/usrp2/fifo/buffer_int2.v
-share/uhd/fpga/usrp2/fifo/buffer_int_tb.v
-share/uhd/fpga/usrp2/fifo/buffer_pool.v
-share/uhd/fpga/usrp2/fifo/buffer_pool_tb.v
-share/uhd/fpga/usrp2/fifo/crossbar36.v
-share/uhd/fpga/usrp2/fifo/dsp_framer36.v
-share/uhd/fpga/usrp2/fifo/fifo19_mux.v
-share/uhd/fpga/usrp2/fifo/fifo19_pad.v
-share/uhd/fpga/usrp2/fifo/fifo19_to_fifo36.v
-share/uhd/fpga/usrp2/fifo/fifo19_to_ll8.v
-share/uhd/fpga/usrp2/fifo/fifo36_demux.v
-share/uhd/fpga/usrp2/fifo/fifo36_mux.v
-share/uhd/fpga/usrp2/fifo/fifo36_to_fifo19.v
-share/uhd/fpga/usrp2/fifo/fifo36_to_fifo72.v
-share/uhd/fpga/usrp2/fifo/fifo36_to_ll8.v
-share/uhd/fpga/usrp2/fifo/fifo72_to_fifo36.v
-share/uhd/fpga/usrp2/fifo/fifo_19to36_tb.v
-share/uhd/fpga/usrp2/fifo/fifo_2clock.v
-share/uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v
-share/uhd/fpga/usrp2/fifo/fifo_cascade.v
-share/uhd/fpga/usrp2/fifo/fifo_long.v
-share/uhd/fpga/usrp2/fifo/fifo_pacer.v
-share/uhd/fpga/usrp2/fifo/fifo_short.v
-share/uhd/fpga/usrp2/fifo/fifo_spec.txt
-share/uhd/fpga/usrp2/fifo/fifo_tb.v
-share/uhd/fpga/usrp2/fifo/ll8_shortfifo.v
-share/uhd/fpga/usrp2/fifo/ll8_to_fifo19.v
-share/uhd/fpga/usrp2/fifo/ll8_to_fifo36.v
-share/uhd/fpga/usrp2/fifo/packet32_tb.v
-share/uhd/fpga/usrp2/fifo/packet_dispatcher36_x3.v
-share/uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v
-share/uhd/fpga/usrp2/fifo/packet_generator.v
-share/uhd/fpga/usrp2/fifo/packet_generator32.v
-share/uhd/fpga/usrp2/fifo/packet_padder36.v
-share/uhd/fpga/usrp2/fifo/packet_router.v
-share/uhd/fpga/usrp2/fifo/packet_tb.v
-share/uhd/fpga/usrp2/fifo/packet_verifier.v
-share/uhd/fpga/usrp2/fifo/packet_verifier32.v
-share/uhd/fpga/usrp2/fifo/resp_packet_padder36.v
-share/uhd/fpga/usrp2/fifo/splitter36.v
-share/uhd/fpga/usrp2/fifo/valve36.v
-share/uhd/fpga/usrp2/gpif/.gitignore
-share/uhd/fpga/usrp2/gpif/Makefile.srcs
-share/uhd/fpga/usrp2/gpif/fifo36_to_gpmc16.v
-share/uhd/fpga/usrp2/gpif/gpif.v
-share/uhd/fpga/usrp2/gpif/gpif_rd.v
-share/uhd/fpga/usrp2/gpif/gpif_tb.v
-share/uhd/fpga/usrp2/gpif/gpif_wr.v
-share/uhd/fpga/usrp2/gpif/gpif_wr_tb.v
-share/uhd/fpga/usrp2/gpif/gpmc16_to_fifo36.v
-share/uhd/fpga/usrp2/gpif/lint
-share/uhd/fpga/usrp2/gpif/packet_padder36.v
-share/uhd/fpga/usrp2/gpif/packet_reframer.v
-share/uhd/fpga/usrp2/gpif/packet_splitter.v
-share/uhd/fpga/usrp2/gpif/packet_splitter_tb.v
-share/uhd/fpga/usrp2/gpif/slave_fifo.v
-share/uhd/fpga/usrp2/gpmc/.gitignore
-share/uhd/fpga/usrp2/gpmc/Makefile.srcs
-share/uhd/fpga/usrp2/gpmc/cross_clock_reader.v
-share/uhd/fpga/usrp2/gpmc/fifo_to_gpmc.v
-share/uhd/fpga/usrp2/gpmc/gpmc.v
-share/uhd/fpga/usrp2/gpmc/gpmc_to_fifo.v
-share/uhd/fpga/usrp2/models/BUFG.v
-share/uhd/fpga/usrp2/models/CY7C1356C/cy1356.inp
-share/uhd/fpga/usrp2/models/CY7C1356C/cy1356.v
-share/uhd/fpga/usrp2/models/CY7C1356C/readme.txt
-share/uhd/fpga/usrp2/models/CY7C1356C/testbench.v
-share/uhd/fpga/usrp2/models/DCM_SP.v
-share/uhd/fpga/usrp2/models/FIFO_GENERATOR_V4_3.v
-share/uhd/fpga/usrp2/models/FIFO_GENERATOR_V6_1.v
-share/uhd/fpga/usrp2/models/IBUFG.v
-share/uhd/fpga/usrp2/models/IBUFGDS.v
-share/uhd/fpga/usrp2/models/IDDR2.v
-share/uhd/fpga/usrp2/models/IOBUF.v
-share/uhd/fpga/usrp2/models/M24LC024B.v
-share/uhd/fpga/usrp2/models/M24LC02B.v
-share/uhd/fpga/usrp2/models/MULT18X18S.v
-share/uhd/fpga/usrp2/models/ODDR2.v
-share/uhd/fpga/usrp2/models/PLL_ADV.v
-share/uhd/fpga/usrp2/models/PLL_BASE.v
-share/uhd/fpga/usrp2/models/RAMB16_S36_S36.v
-share/uhd/fpga/usrp2/models/SRL16E.v
-share/uhd/fpga/usrp2/models/SRLC16E.v
-share/uhd/fpga/usrp2/models/adc_model.v
-share/uhd/fpga/usrp2/models/cpld_model.v
-share/uhd/fpga/usrp2/models/gpmc_model_async.v
-share/uhd/fpga/usrp2/models/gpmc_model_sync.v
-share/uhd/fpga/usrp2/models/idt71v65603s150.v
-share/uhd/fpga/usrp2/models/math_real.v
-share/uhd/fpga/usrp2/models/miim_model.v
-share/uhd/fpga/usrp2/models/phy_sim.v
-share/uhd/fpga/usrp2/models/serdes_model.v
-share/uhd/fpga/usrp2/models/uart_rx.v
-share/uhd/fpga/usrp2/models/xlnx_glbl.v
-share/uhd/fpga/usrp2/opencores/8b10b/.gitignore
-share/uhd/fpga/usrp2/opencores/8b10b/8b10b_a.mem
-share/uhd/fpga/usrp2/opencores/8b10b/README
-share/uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v
-share/uhd/fpga/usrp2/opencores/8b10b/encode_8b10b.v
-share/uhd/fpga/usrp2/opencores/8b10b/validate_8b10b.v
-share/uhd/fpga/usrp2/opencores/Makefile.srcs
-share/uhd/fpga/usrp2/opencores/README
-share/uhd/fpga/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/.gitignore
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v
-share/uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v
-share/uhd/fpga/usrp2/opencores/aemb/sim/.gitignore
-share/uhd/fpga/usrp2/opencores/aemb/sim/CODE_DEBUG.sav
-share/uhd/fpga/usrp2/opencores/aemb/sim/cversim
-share/uhd/fpga/usrp2/opencores/aemb/sim/iversim
-share/uhd/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v
-share/uhd/fpga/usrp2/opencores/aemb/sim/verilog/edk32.v
-share/uhd/fpga/usrp2/opencores/aemb/sw/c/aeMB_testbench.c
-share/uhd/fpga/usrp2/opencores/aemb/sw/c/endian-test.c
-share/uhd/fpga/usrp2/opencores/aemb/sw/c/libaemb.h
-share/uhd/fpga/usrp2/opencores/aemb/sw/gccrom
-share/uhd/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v
-share/uhd/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v
-share/uhd/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v
-share/uhd/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v
-share/uhd/fpga/usrp2/opencores/i2c/doc/i2c_specs.pdf
-share/uhd/fpga/usrp2/opencores/i2c/doc/src/I2C_specs.doc
-share/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v
-share/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v
-share/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v
-share/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v
-share/uhd/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v
-share/uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD
-share/uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
-share/uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
-share/uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd
-share/uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/readme
-share/uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd
-share/uhd/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd
-share/uhd/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key
-share/uhd/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/run
-share/uhd/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h
-share/uhd/fpga/usrp2/opencores/simple_gpio/rtl/simple_gpio.v
-share/uhd/fpga/usrp2/opencores/simple_pic/rtl/simple_pic.v
-share/uhd/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v
-share/uhd/fpga/usrp2/opencores/spi/bench/verilog/tb_spi_top.v
-share/uhd/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v
-share/uhd/fpga/usrp2/opencores/spi/doc/spi.pdf
-share/uhd/fpga/usrp2/opencores/spi/doc/src/spi.doc
-share/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
-share/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
-share/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
-share/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
-share/uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
-share/uhd/fpga/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl
-share/uhd/fpga/usrp2/opencores/spi/sim/rtl_sim/run/run_sim
-share/uhd/fpga/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl
-share/uhd/fpga/usrp2/opencores/spi_boot/COMPILE_LIST
-share/uhd/fpga/usrp2/opencores/spi_boot/COPYING
-share/uhd/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS
-share/uhd/fpga/usrp2/opencores/spi_boot/README
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/architecture.fig
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/initialization.eps
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/initialization.fig
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/memory_organization.eps
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/memory_organization.fig
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/spi_boot.sxw
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/transfer.eps
-share/uhd/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
-share/uhd/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile
-share/uhd/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c
-share/uhd/fpga/usrp2/opencores/wb_zbt/wb_zbt.v
-share/uhd/fpga/usrp2/opencores/zpu/core/zpu_config.vhd
-share/uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd
-share/uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd
-share/uhd/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd
-share/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd
-share/uhd/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd
-share/uhd/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd
-share/uhd/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd
-share/uhd/fpga/usrp2/sdr_lib/.gitignore
-share/uhd/fpga/usrp2/sdr_lib/HB.sav
-share/uhd/fpga/usrp2/sdr_lib/Makefile.srcs
-share/uhd/fpga/usrp2/sdr_lib/SMALL_HB.sav
-share/uhd/fpga/usrp2/sdr_lib/acc.v
-share/uhd/fpga/usrp2/sdr_lib/add2.v
-share/uhd/fpga/usrp2/sdr_lib/add2_and_clip.v
-share/uhd/fpga/usrp2/sdr_lib/add2_and_clip_reg.v
-share/uhd/fpga/usrp2/sdr_lib/add2_and_round.v
-share/uhd/fpga/usrp2/sdr_lib/add2_and_round_reg.v
-share/uhd/fpga/usrp2/sdr_lib/add2_reg.v
-share/uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v
-share/uhd/fpga/usrp2/sdr_lib/cic_decim.v
-share/uhd/fpga/usrp2/sdr_lib/cic_int_shifter.v
-share/uhd/fpga/usrp2/sdr_lib/cic_interp.v
-share/uhd/fpga/usrp2/sdr_lib/cic_strober.v
-share/uhd/fpga/usrp2/sdr_lib/clip.v
-share/uhd/fpga/usrp2/sdr_lib/clip_and_round.v
-share/uhd/fpga/usrp2/sdr_lib/clip_and_round_reg.v
-share/uhd/fpga/usrp2/sdr_lib/clip_reg.v
-share/uhd/fpga/usrp2/sdr_lib/cordic.v
-share/uhd/fpga/usrp2/sdr_lib/cordic_stage.v
-share/uhd/fpga/usrp2/sdr_lib/cordic_z24.v
-share/uhd/fpga/usrp2/sdr_lib/ddc.v
-share/uhd/fpga/usrp2/sdr_lib/ddc_chain.v
-share/uhd/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v
-share/uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v
-share/uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v
-share/uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v
-share/uhd/fpga/usrp2/sdr_lib/dspengine_8to16.v
-share/uhd/fpga/usrp2/sdr_lib/duc.v
-share/uhd/fpga/usrp2/sdr_lib/duc_chain.v
-share/uhd/fpga/usrp2/sdr_lib/dummy_rx.v
-share/uhd/fpga/usrp2/sdr_lib/gen_cordic_consts.py
-share/uhd/fpga/usrp2/sdr_lib/halfband_ideal.v
-share/uhd/fpga/usrp2/sdr_lib/halfband_tb.v
-share/uhd/fpga/usrp2/sdr_lib/hb/acc.v
-share/uhd/fpga/usrp2/sdr_lib/hb/coeff_ram.v
-share/uhd/fpga/usrp2/sdr_lib/hb/coeff_rom.v
-share/uhd/fpga/usrp2/sdr_lib/hb/halfband_decim.v
-share/uhd/fpga/usrp2/sdr_lib/hb/halfband_interp.v
-share/uhd/fpga/usrp2/sdr_lib/hb/hbd_tb/HBD
-share/uhd/fpga/usrp2/sdr_lib/hb/hbd_tb/really_golden
-share/uhd/fpga/usrp2/sdr_lib/hb/hbd_tb/regression
-share/uhd/fpga/usrp2/sdr_lib/hb/hbd_tb/run_hbd
-share/uhd/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v
-share/uhd/fpga/usrp2/sdr_lib/hb/mac.v
-share/uhd/fpga/usrp2/sdr_lib/hb/mult.v
-share/uhd/fpga/usrp2/sdr_lib/hb/ram16_2port.v
-share/uhd/fpga/usrp2/sdr_lib/hb/ram16_2sum.v
-share/uhd/fpga/usrp2/sdr_lib/hb/ram32_2sum.v
-share/uhd/fpga/usrp2/sdr_lib/hb_dec.v
-share/uhd/fpga/usrp2/sdr_lib/hb_dec_tb.v
-share/uhd/fpga/usrp2/sdr_lib/hb_interp.v
-share/uhd/fpga/usrp2/sdr_lib/hb_interp_tb.v
-share/uhd/fpga/usrp2/sdr_lib/hb_tb.v
-share/uhd/fpga/usrp2/sdr_lib/input.dat
-share/uhd/fpga/usrp2/sdr_lib/integrate.v
-share/uhd/fpga/usrp2/sdr_lib/med_hb_int.v
-share/uhd/fpga/usrp2/sdr_lib/output.dat
-share/uhd/fpga/usrp2/sdr_lib/pipectrl.v
-share/uhd/fpga/usrp2/sdr_lib/pipestage.v
-share/uhd/fpga/usrp2/sdr_lib/round.v
-share/uhd/fpga/usrp2/sdr_lib/round_reg.v
-share/uhd/fpga/usrp2/sdr_lib/round_sd.v
-share/uhd/fpga/usrp2/sdr_lib/round_sd_tb.v
-share/uhd/fpga/usrp2/sdr_lib/round_tb.v
-share/uhd/fpga/usrp2/sdr_lib/rssi.v
-share/uhd/fpga/usrp2/sdr_lib/rx_control.v
-share/uhd/fpga/usrp2/sdr_lib/rx_dcoffset.v
-share/uhd/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
-share/uhd/fpga/usrp2/sdr_lib/rx_frontend.v
-share/uhd/fpga/usrp2/sdr_lib/rx_frontend_tb.v
-share/uhd/fpga/usrp2/sdr_lib/sign_extend.v
-share/uhd/fpga/usrp2/sdr_lib/small_hb_dec.v
-share/uhd/fpga/usrp2/sdr_lib/small_hb_dec_tb.v
-share/uhd/fpga/usrp2/sdr_lib/small_hb_int.v
-share/uhd/fpga/usrp2/sdr_lib/small_hb_int_tb.v
-share/uhd/fpga/usrp2/sdr_lib/tx_control.v
-share/uhd/fpga/usrp2/sdr_lib/tx_frontend.v
-share/uhd/fpga/usrp2/serdes/Makefile.srcs
-share/uhd/fpga/usrp2/serdes/serdes.v
-share/uhd/fpga/usrp2/serdes/serdes_fc_rx.v
-share/uhd/fpga/usrp2/serdes/serdes_fc_tx.v
-share/uhd/fpga/usrp2/serdes/serdes_rx.v
-share/uhd/fpga/usrp2/serdes/serdes_tb.v
-share/uhd/fpga/usrp2/serdes/serdes_tx.v
-share/uhd/fpga/usrp2/simple_gemac/.gitignore
-share/uhd/fpga/usrp2/simple_gemac/Makefile.srcs
-share/uhd/fpga/usrp2/simple_gemac/address_filter.v
-share/uhd/fpga/usrp2/simple_gemac/address_filter_promisc.v
-share/uhd/fpga/usrp2/simple_gemac/crc.v
-share/uhd/fpga/usrp2/simple_gemac/delay_line.v
-share/uhd/fpga/usrp2/simple_gemac/eth_tasks.v
-share/uhd/fpga/usrp2/simple_gemac/eth_tasks_f19.v
-share/uhd/fpga/usrp2/simple_gemac/eth_tasks_f36.v
-share/uhd/fpga/usrp2/simple_gemac/ethrx_realign.v
-share/uhd/fpga/usrp2/simple_gemac/ethtx_realign.v
-share/uhd/fpga/usrp2/simple_gemac/flow_ctrl_rx.v
-share/uhd/fpga/usrp2/simple_gemac/flow_ctrl_tx.v
-share/uhd/fpga/usrp2/simple_gemac/ll8_to_txmac.v
-share/uhd/fpga/usrp2/simple_gemac/miim/eth_clockgen.v
-share/uhd/fpga/usrp2/simple_gemac/miim/eth_miim.v
-share/uhd/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v
-share/uhd/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v
-share/uhd/fpga/usrp2/simple_gemac/rxmac_to_ll8.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_rx.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_tb.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_tx.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_wb.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v
-share/uhd/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
-share/uhd/fpga/usrp2/simple_gemac/test_packet.mem
-share/uhd/fpga/usrp2/testbench/.gitignore
-share/uhd/fpga/usrp2/testbench/Makefile
-share/uhd/fpga/usrp2/testbench/README
-share/uhd/fpga/usrp2/testbench/cmdfile
-share/uhd/fpga/usrp2/testbench/single_u2_sim.v
-share/uhd/fpga/usrp2/timing/.gitignore
-share/uhd/fpga/usrp2/timing/Makefile.srcs
-share/uhd/fpga/usrp2/timing/simple_timer.v
-share/uhd/fpga/usrp2/timing/time_64bit.v
-share/uhd/fpga/usrp2/timing/time_compare.v
-share/uhd/fpga/usrp2/timing/time_receiver.v
-share/uhd/fpga/usrp2/timing/time_sender.v
-share/uhd/fpga/usrp2/timing/time_sync.v
-share/uhd/fpga/usrp2/timing/time_transfer_tb.v
-share/uhd/fpga/usrp2/timing/timer.v
-share/uhd/fpga/usrp2/top/.gitignore
-share/uhd/fpga/usrp2/top/B100/.gitignore
-share/uhd/fpga/usrp2/top/B100/B100.ucf
-share/uhd/fpga/usrp2/top/B100/B100.v
-share/uhd/fpga/usrp2/top/B100/Makefile
-share/uhd/fpga/usrp2/top/B100/Makefile.B100
-share/uhd/fpga/usrp2/top/B100/Makefile.B100_2RX
-share/uhd/fpga/usrp2/top/B100/core_compile
-share/uhd/fpga/usrp2/top/B100/timing.ucf
-share/uhd/fpga/usrp2/top/B100/u1plus_core.v
-share/uhd/fpga/usrp2/top/E1x0/.gitignore
-share/uhd/fpga/usrp2/top/E1x0/E1x0.ucf
-share/uhd/fpga/usrp2/top/E1x0/E1x0.v
-share/uhd/fpga/usrp2/top/E1x0/Makefile
-share/uhd/fpga/usrp2/top/E1x0/Makefile.E100
-share/uhd/fpga/usrp2/top/E1x0/Makefile.E110
-share/uhd/fpga/usrp2/top/E1x0/README
-share/uhd/fpga/usrp2/top/E1x0/cmdfile
-share/uhd/fpga/usrp2/top/E1x0/core_compile
-share/uhd/fpga/usrp2/top/E1x0/make.sim
-share/uhd/fpga/usrp2/top/E1x0/tb_u1e.v
-share/uhd/fpga/usrp2/top/E1x0/timing.ucf
-share/uhd/fpga/usrp2/top/Makefile.common
-share/uhd/fpga/usrp2/top/N2x0/.gitignore
-share/uhd/fpga/usrp2/top/N2x0/Makefile
-share/uhd/fpga/usrp2/top/N2x0/Makefile.N200R3
-share/uhd/fpga/usrp2/top/N2x0/Makefile.N200R4
-share/uhd/fpga/usrp2/top/N2x0/Makefile.N210R3
-share/uhd/fpga/usrp2/top/N2x0/Makefile.N210R4
-share/uhd/fpga/usrp2/top/N2x0/bootloader.rmi
-share/uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v
-share/uhd/fpga/usrp2/top/N2x0/u2plus.ucf
-share/uhd/fpga/usrp2/top/N2x0/u2plus.v
-share/uhd/fpga/usrp2/top/N2x0/u2plus_core.v
-share/uhd/fpga/usrp2/top/USRP2/.gitignore
-share/uhd/fpga/usrp2/top/USRP2/Makefile
-share/uhd/fpga/usrp2/top/USRP2/u2_core.v
-share/uhd/fpga/usrp2/top/USRP2/u2_rev3.ucf
-share/uhd/fpga/usrp2/top/USRP2/u2_rev3.v
-share/uhd/fpga/usrp2/top/extract_usage.py
-share/uhd/fpga/usrp2/top/impactor.sh
-share/uhd/fpga/usrp2/top/python/check_inout.py
-share/uhd/fpga/usrp2/top/python/check_timing.py
-share/uhd/fpga/usrp2/top/tcl/ise_helper.tcl
-share/uhd/fpga/usrp2/udp/Makefile.srcs
-share/uhd/fpga/usrp2/udp/add_onescomp.v
-share/uhd/fpga/usrp2/udp/fifo19_rxrealign.v
-share/uhd/fpga/usrp2/udp/prot_eng_rx.v
-share/uhd/fpga/usrp2/udp/prot_eng_tx.v
-share/uhd/fpga/usrp2/udp/prot_eng_tx_tb.v
-share/uhd/fpga/usrp2/udp/udp_wrapper.v
-share/uhd/fpga/usrp2/vrt/.gitignore
-share/uhd/fpga/usrp2/vrt/Makefile.srcs
-share/uhd/fpga/usrp2/vrt/gen_context_pkt.v
-share/uhd/fpga/usrp2/vrt/trigger_context_pkt.v
-share/uhd/fpga/usrp2/vrt/vita_packet_demux36.v
-share/uhd/fpga/usrp2/vrt/vita_pkt_gen.v
-share/uhd/fpga/usrp2/vrt/vita_rx.build
-share/uhd/fpga/usrp2/vrt/vita_rx_chain.v
-share/uhd/fpga/usrp2/vrt/vita_rx_control.v
-share/uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v
-share/uhd/fpga/usrp2/vrt/vita_rx_framer.v
-share/uhd/fpga/usrp2/vrt/vita_rx_tb.v
-share/uhd/fpga/usrp2/vrt/vita_tx.build
-share/uhd/fpga/usrp2/vrt/vita_tx_chain.v
-share/uhd/fpga/usrp2/vrt/vita_tx_control.v
-share/uhd/fpga/usrp2/vrt/vita_tx_deframer.v
-share/uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v
-share/uhd/fpga/usrp2/vrt/vita_tx_tb.v
-share/uhd/fpga/usrp3/README.txt
-share/uhd/fpga/usrp3/lib/axi/Makefile.srcs
-share/uhd/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v
-share/uhd/fpga/usrp3/lib/axi/axi_chdr_test_pattern.v
-share/uhd/fpga/usrp3/lib/axi/axi_defs.v
-share/uhd/fpga/usrp3/lib/axi/axi_dma_master.v
-share/uhd/fpga/usrp3/lib/axi/axi_dma_master_tb.v
-share/uhd/fpga/usrp3/lib/axi/axi_dram_fifo.v
-share/uhd/fpga/usrp3/lib/axi/axi_dram_fifo_tb.v
-share/uhd/fpga/usrp3/lib/axi/axi_embed_tlast.v
-share/uhd/fpga/usrp3/lib/axi/axi_extract_tlast.v
-share/uhd/fpga/usrp3/lib/axi/axi_fast_extract_tlast.v
-share/uhd/fpga/usrp3/lib/axi/axi_fast_fifo.v
-share/uhd/fpga/usrp3/lib/axi/axi_lite_slave.v
-share/uhd/fpga/usrp3/lib/control/Makefile.srcs
-share/uhd/fpga/usrp3/lib/control/README.txt
-share/uhd/fpga/usrp3/lib/control/arb_qualify_master.v
-share/uhd/fpga/usrp3/lib/control/axi_crossbar.v
-share/uhd/fpga/usrp3/lib/control/axi_crossbar_tb.v
-share/uhd/fpga/usrp3/lib/control/axi_fifo_header.v
-share/uhd/fpga/usrp3/lib/control/axi_forwarding_cam.v
-share/uhd/fpga/usrp3/lib/control/axi_slave_mux.v
-share/uhd/fpga/usrp3/lib/control/axi_test_vfifo.v
-share/uhd/fpga/usrp3/lib/control/binary_encoder.v
-share/uhd/fpga/usrp3/lib/control/cvita_uart.v
-share/uhd/fpga/usrp3/lib/control/dram_2port.v
-share/uhd/fpga/usrp3/lib/control/filter_bad_sid.v
-share/uhd/fpga/usrp3/lib/control/gpio_atr.v
-share/uhd/fpga/usrp3/lib/control/por_gen.v
-share/uhd/fpga/usrp3/lib/control/radio_ctrl_proc.v
-share/uhd/fpga/usrp3/lib/control/radio_ctrl_proc_tb.v
-share/uhd/fpga/usrp3/lib/control/ram_2port.v
-share/uhd/fpga/usrp3/lib/control/reset_sync.v
-share/uhd/fpga/usrp3/lib/control/serial_to_settings.v
-share/uhd/fpga/usrp3/lib/control/serial_to_settings_tb.v
-share/uhd/fpga/usrp3/lib/control/setting_reg.v
-share/uhd/fpga/usrp3/lib/control/settings_bus_crossclock.v
-share/uhd/fpga/usrp3/lib/control/simple_i2c_core.v
-share/uhd/fpga/usrp3/lib/control/simple_spi_core.v
-share/uhd/fpga/usrp3/lib/coregen/.gitignore
-share/uhd/fpga/usrp3/lib/coregen/README.txt
-share/uhd/fpga/usrp3/lib/dsp/Makefile.srcs
-share/uhd/fpga/usrp3/lib/dsp/README.txt
-share/uhd/fpga/usrp3/lib/dsp/acc.v
-share/uhd/fpga/usrp3/lib/dsp/add2.v
-share/uhd/fpga/usrp3/lib/dsp/add2_and_clip.v
-share/uhd/fpga/usrp3/lib/dsp/add2_and_clip_reg.v
-share/uhd/fpga/usrp3/lib/dsp/add2_and_round.v
-share/uhd/fpga/usrp3/lib/dsp/add2_and_round_reg.v
-share/uhd/fpga/usrp3/lib/dsp/add2_reg.v
-share/uhd/fpga/usrp3/lib/dsp/cic_dec_shifter.v
-share/uhd/fpga/usrp3/lib/dsp/cic_decim.v
-share/uhd/fpga/usrp3/lib/dsp/cic_int_shifter.v
-share/uhd/fpga/usrp3/lib/dsp/cic_interp.v
-share/uhd/fpga/usrp3/lib/dsp/cic_strober.v
-share/uhd/fpga/usrp3/lib/dsp/clip.v
-share/uhd/fpga/usrp3/lib/dsp/clip_reg.v
-share/uhd/fpga/usrp3/lib/dsp/cordic_stage.v
-share/uhd/fpga/usrp3/lib/dsp/cordic_z24.v
-share/uhd/fpga/usrp3/lib/dsp/ddc_chain.v
-share/uhd/fpga/usrp3/lib/dsp/ddc_chain_x300.v
-share/uhd/fpga/usrp3/lib/dsp/ddc_chain_x300_tb.v
-share/uhd/fpga/usrp3/lib/dsp/duc_chain.v
-share/uhd/fpga/usrp3/lib/dsp/hb_dec.v
-share/uhd/fpga/usrp3/lib/dsp/hb_interp.v
-share/uhd/fpga/usrp3/lib/dsp/round.v
-share/uhd/fpga/usrp3/lib/dsp/round_reg.v
-share/uhd/fpga/usrp3/lib/dsp/round_sd.v
-share/uhd/fpga/usrp3/lib/dsp/rx_dcoffset.v
-share/uhd/fpga/usrp3/lib/dsp/rx_frontend.v
-share/uhd/fpga/usrp3/lib/dsp/rx_frontend_tb.v
-share/uhd/fpga/usrp3/lib/dsp/sign_extend.v
-share/uhd/fpga/usrp3/lib/dsp/small_hb_dec.v
-share/uhd/fpga/usrp3/lib/dsp/small_hb_int.v
-share/uhd/fpga/usrp3/lib/dsp/srl.v
-share/uhd/fpga/usrp3/lib/dsp/tx_frontend.v
-share/uhd/fpga/usrp3/lib/fifo/Makefile.srcs
-share/uhd/fpga/usrp3/lib/fifo/axi_demux4.v
-share/uhd/fpga/usrp3/lib/fifo/axi_demux8.v
-share/uhd/fpga/usrp3/lib/fifo/axi_fifo.v
-share/uhd/fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v
-share/uhd/fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v
-share/uhd/fpga/usrp3/lib/fifo/axi_fifo_2clk.v
-share/uhd/fpga/usrp3/lib/fifo/axi_fifo_32_64_tb.v
-share/uhd/fpga/usrp3/lib/fifo/axi_fifo_short.v
-share/uhd/fpga/usrp3/lib/fifo/axi_fifo_tb.v
-share/uhd/fpga/usrp3/lib/fifo/axi_filter_mux4.v
-share/uhd/fpga/usrp3/lib/fifo/axi_loopback.v
-share/uhd/fpga/usrp3/lib/fifo/axi_mux4.v
-share/uhd/fpga/usrp3/lib/fifo/axi_mux8.v
-share/uhd/fpga/usrp3/lib/fifo/axi_packet_gate.v
-share/uhd/fpga/usrp3/lib/fifo/axi_packet_gate_tb.v
-share/uhd/fpga/usrp3/lib/fifo/monitor_axi_fifo.v
-share/uhd/fpga/usrp3/lib/fifo/shortfifo.v
-share/uhd/fpga/usrp3/lib/gpif2/Makefile.srcs
-share/uhd/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v
-share/uhd/fpga/usrp3/lib/gpif2/gpif2_error_checker.v
-share/uhd/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v
-share/uhd/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v
-share/uhd/fpga/usrp3/lib/io_port2/.gitignore
-share/uhd/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.ngc
-share/uhd/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v
-share/uhd/fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.vh
-share/uhd/fpga/usrp3/lib/io_port2/Makefile.srcs
-share/uhd/fpga/usrp3/lib/io_port2/create-lvbitx.py
-share/uhd/fpga/usrp3/lib/io_port2/data_swapper_64.v
-share/uhd/fpga/usrp3/lib/io_port2/ioport2_msg_codec.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_axi_wb_conv.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_basic_regs.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_dma_ctrl_tb.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter_tb.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_pkt_route_specifier.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_wb_reg_core.v
-share/uhd/fpga/usrp3/lib/io_port2/pcie_wb_reg_core_tb.v
-share/uhd/fpga/usrp3/lib/packet_proc/.gitignore
-share/uhd/fpga/usrp3/lib/packet_proc/Makefile.srcs
-share/uhd/fpga/usrp3/lib/packet_proc/axis_packet_debug.v
-share/uhd/fpga/usrp3/lib/packet_proc/chdr_eth_framer.v
-share/uhd/fpga/usrp3/lib/packet_proc/compressed_vita_to_vrlp.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_chunker.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_dechunker.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_insert_tlast.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_insert_tlast_tb.v
-share/uhd/fpga/usrp3/lib/packet_proc/cvita_packet_debug.v
-share/uhd/fpga/usrp3/lib/packet_proc/eth_dispatch.v
-share/uhd/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v
-share/uhd/fpga/usrp3/lib/packet_proc/eth_interface.v
-share/uhd/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v
-share/uhd/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v
-share/uhd/fpga/usrp3/lib/packet_proc/source_flow_control.v
-share/uhd/fpga/usrp3/lib/packet_proc/source_flow_control_tb.v
-share/uhd/fpga/usrp3/lib/packet_proc/vita_eth_framer.v
-share/uhd/fpga/usrp3/lib/packet_proc/vrlp_eth_framer.v
-share/uhd/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita.v
-share/uhd/fpga/usrp3/lib/packet_proc/vrlp_to_compressed_vita_tb.v
-share/uhd/fpga/usrp3/lib/sim/axi_chdr_tb.v
-share/uhd/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog
-share/uhd/fpga/usrp3/lib/sim/axi_crossbar/run_sim
-share/uhd/fpga/usrp3/lib/sim/axi_crossbar/simulation_script.v
-share/uhd/fpga/usrp3/lib/sim/axi_dram_fifo/default.wcfg
-share/uhd/fpga/usrp3/lib/sim/axi_dram_fifo/run_isim
-share/uhd/fpga/usrp3/lib/sim/axi_fifo/run_sim
-share/uhd/fpga/usrp3/lib/sim/axi_probe_tb.v
-share/uhd/fpga/usrp3/lib/sim/eth_dispatch/default.wcfg
-share/uhd/fpga/usrp3/lib/sim/eth_dispatch/run_sim
-share/uhd/fpga/usrp3/lib/sim/eth_dispatch/simulation_script.v
-share/uhd/fpga/usrp3/lib/sim/source_flow_control/test_window/default.wcfg
-share/uhd/fpga/usrp3/lib/sim/source_flow_control/test_window/run_isim
-share/uhd/fpga/usrp3/lib/sim/source_flow_control/test_window/run_iverilog
-share/uhd/fpga/usrp3/lib/sim/tx/.gitignore
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog
-share/uhd/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v
-share/uhd/fpga/usrp3/lib/simple_gemac/.gitignore
-share/uhd/fpga/usrp3/lib/simple_gemac/Makefile.srcs
-share/uhd/fpga/usrp3/lib/simple_gemac/address_filter.v
-share/uhd/fpga/usrp3/lib/simple_gemac/address_filter_promisc.v
-share/uhd/fpga/usrp3/lib/simple_gemac/axi64_to_ll8.v
-share/uhd/fpga/usrp3/lib/simple_gemac/crc.v
-share/uhd/fpga/usrp3/lib/simple_gemac/delay_line.v
-share/uhd/fpga/usrp3/lib/simple_gemac/eth_tasks.v
-share/uhd/fpga/usrp3/lib/simple_gemac/flow_ctrl_rx.v
-share/uhd/fpga/usrp3/lib/simple_gemac/flow_ctrl_tx.v
-share/uhd/fpga/usrp3/lib/simple_gemac/ll8_to_axi64.v
-share/uhd/fpga/usrp3/lib/simple_gemac/ll8_to_axi64_tb.v
-share/uhd/fpga/usrp3/lib/simple_gemac/ll8_to_txmac.v
-share/uhd/fpga/usrp3/lib/simple_gemac/mdio.v
-share/uhd/fpga/usrp3/lib/simple_gemac/rxmac_to_ll8.v
-share/uhd/fpga/usrp3/lib/simple_gemac/simple_gemac.v
-share/uhd/fpga/usrp3/lib/simple_gemac/simple_gemac_rx.v
-share/uhd/fpga/usrp3/lib/simple_gemac/simple_gemac_tb.v
-share/uhd/fpga/usrp3/lib/simple_gemac/simple_gemac_tx.v
-share/uhd/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.build
-share/uhd/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.v
-share/uhd/fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper_tb.v
-share/uhd/fpga/usrp3/lib/simple_gemac/test_packet.mem
-share/uhd/fpga/usrp3/lib/timing/Makefile.srcs
-share/uhd/fpga/usrp3/lib/timing/pps.v
-share/uhd/fpga/usrp3/lib/timing/time_compare.v
-share/uhd/fpga/usrp3/lib/timing/time_transfer_tb.v
-share/uhd/fpga/usrp3/lib/timing/timekeeper.v
-share/uhd/fpga/usrp3/lib/vita/.gitignore
-share/uhd/fpga/usrp3/lib/vita/Makefile.srcs
-share/uhd/fpga/usrp3/lib/vita/README.txt
-share/uhd/fpga/usrp3/lib/vita/binary_encoder.v
-share/uhd/fpga/usrp3/lib/vita/build_12_to_16
-share/uhd/fpga/usrp3/lib/vita/build_16_to_12
-share/uhd/fpga/usrp3/lib/vita/build_16_to_8
-share/uhd/fpga/usrp3/lib/vita/build_8_to_16
-share/uhd/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v
-share/uhd/fpga/usrp3/lib/vita/chdr_12sc_to_16sc_tb.v
-share/uhd/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v
-share/uhd/fpga/usrp3/lib/vita/chdr_16sc_to_12sc_tb.v
-share/uhd/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v
-share/uhd/fpga/usrp3/lib/vita/chdr_16sc_to_32f_tb.v
-share/uhd/fpga/usrp3/lib/vita/chdr_16sc_to_8sc.v
-share/uhd/fpga/usrp3/lib/vita/chdr_16sc_to_8sc_tb.v
-share/uhd/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v
-share/uhd/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v
-share/uhd/fpga/usrp3/lib/vita/chdr_32f_to_16sc_tb.v
-share/uhd/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.hex
-share/uhd/fpga/usrp3/lib/vita/chdr_8sc_to_16sc.v
-share/uhd/fpga/usrp3/lib/vita/chdr_8sc_to_16sc_tb.v
-share/uhd/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v
-share/uhd/fpga/usrp3/lib/vita/context_packet_gen.v
-share/uhd/fpga/usrp3/lib/vita/float_to_iq.v
-share/uhd/fpga/usrp3/lib/vita/float_to_iq_tb.v
-share/uhd/fpga/usrp3/lib/vita/from12_to_x.hex
-share/uhd/fpga/usrp3/lib/vita/from16_to_x.hex
-share/uhd/fpga/usrp3/lib/vita/from8_to_x.hex
-share/uhd/fpga/usrp3/lib/vita/generate_bits.cpp
-share/uhd/fpga/usrp3/lib/vita/iq_to_float.v
-share/uhd/fpga/usrp3/lib/vita/iq_to_float_input.txt
-share/uhd/fpga/usrp3/lib/vita/iq_to_float_output.txt
-share/uhd/fpga/usrp3/lib/vita/iq_to_float_tb.v
-share/uhd/fpga/usrp3/lib/vita/new_rx_control.v
-share/uhd/fpga/usrp3/lib/vita/new_rx_framer.v
-share/uhd/fpga/usrp3/lib/vita/new_rx_tb.v
-share/uhd/fpga/usrp3/lib/vita/new_tx_control.v
-share/uhd/fpga/usrp3/lib/vita/new_tx_control_tb.v
-share/uhd/fpga/usrp3/lib/vita/new_tx_deframer.v
-share/uhd/fpga/usrp3/lib/vita/new_tx_tb.v
-share/uhd/fpga/usrp3/lib/vita/trigger_context_pkt.v
-share/uhd/fpga/usrp3/lib/vita/tx_responder.v
-share/uhd/fpga/usrp3/lib/wishbone/Makefile.srcs
-share/uhd/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v
-share/uhd/fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v
-share/uhd/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v
-share/uhd/fpga/usrp3/lib/wishbone/i2c_master_defines.v
-share/uhd/fpga/usrp3/lib/wishbone/i2c_master_top.v
-share/uhd/fpga/usrp3/lib/wishbone/settings_bus.v
-share/uhd/fpga/usrp3/lib/wishbone/settings_readback.v
-share/uhd/fpga/usrp3/lib/wishbone/simple_uart.v
-share/uhd/fpga/usrp3/lib/wishbone/simple_uart_rx.v
-share/uhd/fpga/usrp3/lib/wishbone/simple_uart_tb.v
-share/uhd/fpga/usrp3/lib/wishbone/simple_uart_tx.v
-share/uhd/fpga/usrp3/lib/wishbone/wb_1master.v
-share/uhd/fpga/usrp3/lib/xge/Makefile.srcs
-share/uhd/fpga/usrp3/lib/xge/README.txt
-share/uhd/fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
-share/uhd/fpga/usrp3/lib/xge/rtl/include/CRC32_D64.v
-share/uhd/fpga/usrp3/lib/xge/rtl/include/CRC32_D8.v
-share/uhd/fpga/usrp3/lib/xge/rtl/include/defines.v
-share/uhd/fpga/usrp3/lib/xge/rtl/include/timescale.v
-share/uhd/fpga/usrp3/lib/xge/rtl/include/utils.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D64.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/CRC32_D8.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/defines.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/fault_sm.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/generic_fifo_ctrl.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_medium.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_small.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/generic_mem_xilinx_block.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/meta_sync.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/meta_sync_single.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/rx_data_fifo.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/rx_enqueue.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/rx_hold_fifo.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_core.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_wb.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/sync_clk_xgmii_tx.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/timescale.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/tx_data_fifo.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/tx_dequeue.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/tx_enqueue.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/tx_hold_fifo.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/utils.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/wishbone_if.v
-share/uhd/fpga/usrp3/lib/xge/rtl/verilog/xge_mac.v
-share/uhd/fpga/usrp3/lib/xge/sim/verilog/xge_mac.prj
-share/uhd/fpga/usrp3/lib/xge/tbench/verilog/packets_tx.txt
-share/uhd/fpga/usrp3/lib/xge/tbench/verilog/tb_xge_mac.v
-share/uhd/fpga/usrp3/lib/xge_interface/Makefile.srcs
-share/uhd/fpga/usrp3/lib/xge_interface/axi64_to_xge64.v
-share/uhd/fpga/usrp3/lib/xge_interface/axi_count_packets_in_fifo.v
-share/uhd/fpga/usrp3/lib/xge_interface/xge64_to_axi64.v
-share/uhd/fpga/usrp3/lib/xge_interface/xge_handshake.v
-share/uhd/fpga/usrp3/lib/xge_interface/xge_mac_wrapper.v
-share/uhd/fpga/usrp3/lib/zpu/Makefile.srcs
-share/uhd/fpga/usrp3/lib/zpu/core/zpu_config.vhd
-share/uhd/fpga/usrp3/lib/zpu/core/zpu_core.vhd
-share/uhd/fpga/usrp3/lib/zpu/core/zpupkg.vhd
-share/uhd/fpga/usrp3/lib/zpu/wishbone/wishbone_pkg.vhd
-share/uhd/fpga/usrp3/lib/zpu/wishbone/zpu_system.vhd
-share/uhd/fpga/usrp3/lib/zpu/wishbone/zpu_wb_bridge.vhd
-share/uhd/fpga/usrp3/lib/zpu/zpu_top_pkg.vhd
-share/uhd/fpga/usrp3/lib/zpu/zpu_wb_top.vhd
-share/uhd/fpga/usrp3/lib/zynq_fifo/.gitignore
-share/uhd/fpga/usrp3/lib/zynq_fifo/Makefile.srcs
-share/uhd/fpga/usrp3/lib/zynq_fifo/zf_arbiter.v
-share/uhd/fpga/usrp3/lib/zynq_fifo/zf_host_to_stream.v
-share/uhd/fpga/usrp3/lib/zynq_fifo/zf_slave_readback.v
-share/uhd/fpga/usrp3/lib/zynq_fifo/zf_slave_settings.v
-share/uhd/fpga/usrp3/lib/zynq_fifo/zf_stream_to_host.v
-share/uhd/fpga/usrp3/lib/zynq_fifo/zynq_fifo_top.v
-share/uhd/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg
-share/uhd/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim
-share/uhd/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog
-share/uhd/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v
-share/uhd/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg
-share/uhd/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim
-share/uhd/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v
-share/uhd/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/default.wcfg
-share/uhd/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/run_isim
-share/uhd/fpga/usrp3/sim/axi_dram_fifo/sim_sram_1/simulation_script.v
-share/uhd/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/Default.wcfg
-share/uhd/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/run_isim
-share/uhd/fpga/usrp3/sim/axi_dram_fifo/sim_sram_2/simulation_script.v
-share/uhd/fpga/usrp3/sim/b2x0/sim_b2x0_1/run_isim
-share/uhd/fpga/usrp3/sim/ddc_chain_x300/dctest/.gitignore
-share/uhd/fpga/usrp3/sim/ddc_chain_x300/dctest/DDC.sav
-share/uhd/fpga/usrp3/sim/ddc_chain_x300/dctest/run_isim
-share/uhd/fpga/usrp3/sim/ddc_chain_x300/dctest/simcmds.tcl
-share/uhd/fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore
-share/uhd/fpga/usrp3/sim/duc_chain_x300/dctest/run_isim
-share/uhd/fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl
-share/uhd/fpga/usrp3/sim/math.v
-share/uhd/fpga/usrp3/sim/serial_to_settings/serial_settings_tasks.v
-share/uhd/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/default.wcfg
-share/uhd/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/run_isim
-share/uhd/fpga/usrp3/sim/serial_to_settings/sim_serial_to_settings_1/simulation_script.v
-share/uhd/fpga/usrp3/sim/task_library.v
-share/uhd/fpga/usrp3/top/Makefile.common
-share/uhd/fpga/usrp3/top/README.txt
-share/uhd/fpga/usrp3/top/b200/.gitignore
-share/uhd/fpga/usrp3/top/b200/Makefile
-share/uhd/fpga/usrp3/top/b200/Makefile.b200.inc
-share/uhd/fpga/usrp3/top/b200/S6CLK2PIN.v
-share/uhd/fpga/usrp3/top/b200/b200.ucf
-share/uhd/fpga/usrp3/top/b200/b200.v
-share/uhd/fpga/usrp3/top/b200/b200_core.v
-share/uhd/fpga/usrp3/top/b200/b200_tb.v
-share/uhd/fpga/usrp3/top/b200/catcap_ddr_cmos.v
-share/uhd/fpga/usrp3/top/b200/catcap_tb.build
-share/uhd/fpga/usrp3/top/b200/catcap_tb.v
-share/uhd/fpga/usrp3/top/b200/catcodec_ddr_cmos.v
-share/uhd/fpga/usrp3/top/b200/catgen_ddr_cmos.v
-share/uhd/fpga/usrp3/top/b200/catgen_tb.build
-share/uhd/fpga/usrp3/top/b200/catgen_tb.v
-share/uhd/fpga/usrp3/top/b200/check.sh
-share/uhd/fpga/usrp3/top/b200/core_compile
-share/uhd/fpga/usrp3/top/b200/coregen/.gitignore
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.gise
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xise
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.gise
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xise
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.gise
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.v
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen.xise
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt
-share/uhd/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.asy
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.gise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.v
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.veo
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.xco
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon.xise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.gise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.v
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.veo
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xco
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128.xise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128_flist.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.gise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.gise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xise
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/coregen.cgp
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.gise
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk.gise
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xise
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key
-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl
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-share/uhd/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg
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-share/uhd/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml
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-share/uhd/fpga/usrp3/top/b200/planahead/planahead.ppr
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.begin.rst
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.end.rst
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-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd
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-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl
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-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh
-share/uhd/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf
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-share/uhd/fpga/usrp3/top/b200/radio_b200.v
-share/uhd/fpga/usrp3/top/b200/timing.ucf
-share/uhd/fpga/usrp3/top/impactor.sh
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-share/uhd/fpga/usrp3/top/python/check_inout.py
-share/uhd/fpga/usrp3/top/python/check_timing.py
-share/uhd/fpga/usrp3/top/tcl/ise_helper.tcl
-share/uhd/fpga/usrp3/top/x300/.gitignore
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-share/uhd/fpga/usrp3/top/x300/bus_int.v
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-share/uhd/fpga/usrp3/top/x300/capture_ddrlvds.v
-share/uhd/fpga/usrp3/top/x300/coregen/.gitignore
-share/uhd/fpga/usrp3/top/x300/coregen/Makefile.srcs
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64.asy
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64.gise
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64.v
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-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/blk_mem_gen_v7_3_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/doc/blk_mem_gen_v7_3_vinfo.html
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/doc/pg058-blk-mem-gen.pdf
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.vhd
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-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/example_design/axi4_bram_1kx64_prod.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/implement/implement.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/implement/planAhead_ise.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/implement/planAhead_ise.tcl
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-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/simulation/addr_gen.vhd
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-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/simulation/axi4_bram_1kx64_tb.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/simulation/axi_checker.vhd
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-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_isim.sh
-share/uhd/fpga/usrp3/top/x300/coregen/axi4_bram_1kx64/simulation/timing/simulate_mti.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/axi64_4k_2clk_fifo/doc/pg057-fifo-generator.pdf
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-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/doc/fifo_generator_v9_3_vinfo.html
-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/doc/pg057-fifo-generator.pdf
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-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/example_design/axi64_8k_2clk_fifo_exdes.vhd
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-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/simulation/axi64_8k_2clk_fifo_pctrl.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/simulation/axi64_8k_2clk_fifo_pkg.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/simulation/axi64_8k_2clk_fifo_rng.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/simulation/axi64_8k_2clk_fifo_synth.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/simulation/axi64_8k_2clk_fifo_tb.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/axi64_8k_2clk_fifo/simulation/functional/simulate_isim.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_axic_sync_clock_converter.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_axilite_conv.v
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-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_converter_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_crossbar.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_crossbar_sasd.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_data_fifo_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_decerr_slave.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_fifo_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_mux_enc.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_ndeep_srl.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_nto1_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_protocol_conv_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_r_axi3_conv.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_r_downsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_r_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_register_slice_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_si_transactor.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_splitter.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_w_axi3_conv.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_w_downsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_w_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_wdata_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128/hdl/verilog/ict106_wdata_router.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128_sim.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_2x64_128_synth.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.asy
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.gise
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.veo
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.xco
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128.xise
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/doc/axi_interconnect_v1_06_a_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/doc/axi_interconnect_v1_06_a_vinfo.html
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/doc/ds768_axi_interconnect.pdf
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/generate/axi_interconnect_v1_06_a_ucfgen.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/axi_interconnect_v1_06_a.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_a_axi3_conv.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_a_downsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_a_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_addr_arbiter.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_addr_arbiter_sasd.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_addr_decoder.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_arbiter_resp.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi3_conv.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_clock_converter.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_crossbar.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_data_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_downsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_interconnect.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_protocol_converter.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_reg_srl_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_sample_cycle_ratio.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_srl_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_sync_clock_converter.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axilite_conv.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_b_downsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_latch_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_latch_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_command_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_mask.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_mask_static.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel_mask.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel_mask_static.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel_static.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_static.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_converter_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_crossbar.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_crossbar_sasd.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_data_fifo_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_decerr_slave.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_fifo_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_mux_enc.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_ndeep_srl.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_nto1_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_protocol_conv_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_r_axi3_conv.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_r_downsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_r_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_register_slice_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_si_transactor.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_splitter.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_w_axi3_conv.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_w_downsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_w_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_wdata_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128/hdl/verilog/ict106_wdata_router.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128_sim.v
-share/uhd/fpga/usrp3/top/x300/coregen/axi_intercon_4x64_128_synth.v
-share/uhd/fpga/usrp3/top/x300/coregen/bootram.asy
-share/uhd/fpga/usrp3/top/x300/coregen/bootram.coe
-share/uhd/fpga/usrp3/top/x300/coregen/bootram.gise
-share/uhd/fpga/usrp3/top/x300/coregen/bootram.mif
-share/uhd/fpga/usrp3/top/x300/coregen/bootram.v
-share/uhd/fpga/usrp3/top/x300/coregen/bootram.veo
-share/uhd/fpga/usrp3/top/x300/coregen/bootram.xco
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/blk_mem_gen_v7_3_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/doc/blk_mem_gen_v7_3_vinfo.html
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/doc/pg058-blk-mem-gen.pdf
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_prod.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/implement/implement.bat
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/implement/implement.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.bat
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/implement/xst.prj
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/implement/xst.scr
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/addr_gen.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_stim_gen.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_tb_pkg.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_synth.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_tb.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/checker.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/data_gen.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simcmds.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_isim.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.bat
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.do
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_ncsim.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_vcs.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/ucli_commands.key
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/vcs_session.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_mti.do
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_ncsim.sv
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/random.vhd
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simcmds.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_isim.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.bat
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.do
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_ncsim.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_vcs.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/ucli_commands.key
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/vcs_session.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_mti.do
-share/uhd/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_ncsim.sv
-share/uhd/fpga/usrp3/top/x300/coregen/bootram_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/bootram_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.asy
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.gise
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.veo
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.xco
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen.xise
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/doc/pg065_clk_wiz.pdf
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.v
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/implement.bat
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/implement.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/planAhead_ise.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/planAhead_ise.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/planAhead_rdn.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/planAhead_rdn.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/xst.prj
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/implement/xst.scr
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/functional/simcmds.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/functional/simulate_isim.bat
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/functional/simulate_isim.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/functional/simulate_mti.bat
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/functional/simulate_mti.do
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-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/simulate_mti.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/simulate_vcs.sh
-share/uhd/fpga/usrp3/top/x300/coregen/bus_clk_gen/simulation/timing/ucli_commands.key
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/constraints/ddr3_32bit.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/constraints/ddr3_32bit.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/log.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_arb_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_arb_select.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_common.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_state.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_col_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_mc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_rank_common.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_rank_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ddr3_32bit.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_dec_fix.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_merge_enc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_32bit_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface.veo
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/datasheet.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/ddr3_interface.csv
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/docs/phy_only_support_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/docs/ug586_7Series_MIS.pdf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/log.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/compatible_ucf/xc7k325tffg900_pkg.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/compatible_ucf/xc7k325tffg900_pkg.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/coregen.cgc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/coregen.cgp
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/create_ise.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.constraints/ddr_icon.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.constraints/ddr_icon.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon.xco
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_icon_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_basic.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_basic.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_basic.constraints/ddr_ila_basic.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_basic.constraints/ddr_ila_basic.xdc
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_wrpath.xise
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_wrpath_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_wrpath_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_ila_wrpath_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.constraints/ddr_vio_async_in_sync_out.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.constraints/ddr_vio_async_in_sync_out.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out_cg.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_async_in_sync_out_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.constraints/ddr_vio_sync_async_out72.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.constraints/ddr_vio_sync_async_out72.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72.xco
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72_cg.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ddr_vio_sync_async_out72_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.bgn
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.bit
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.bld
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.cpj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.drc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.ncd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.ngd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.pad
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.par
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.pcf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.ptwx
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.syr
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.twr
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.twx
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.unroutes
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top.xdc
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_bitgen.xwbt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_map.map
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_map.mrp
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_map.ncd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_map.ngm
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_map.xrpt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_ngdbuild.xrpt
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/example_top_par.xrpt
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/ise_flow.sh
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/makeproj.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/par_usage_statistics.html
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/rem_files.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/rem_files.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/set_ise_prop.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/vivado.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/vivado_gui.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/xlnx_auto_0_xdb/cst.xbcd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/par/xst_options.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/ddr2_ddr3_chipscope.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/example_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/mig_7series_v1_8_chk_win.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_tg.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_data_gen_chk.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_tg.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/ddr3_model.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/ddr3_model_parameters.vh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/sim.do
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/sim_tb_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/wiredly.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/xsim_files.prj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/xsim_options.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/sim/xsim_run.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/synth/_ngo/netlist.lst
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/synth/example_top.lso
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/example_design/synth/example_top.prj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/mig.prj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/constraints/compatible_ucf/xc7k325tffg900_pkg.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/constraints/compatible_ucf/xc7k325tffg900_pkg.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/constraints/ddr3_interface.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/constraints/ddr3_interface.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/log.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_arb_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_arb_select.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_bank_common.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_bank_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_bank_state.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_col_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_mc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_rank_common.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_rank_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ddr3_interface.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ecc/mig_7series_v1_8_ecc_dec_fix.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ecc/mig_7series_v1_8_ecc_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ecc/mig_7series_v1_8_ecc_merge_enc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ui/mig_7series_v1_8_ui_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast.veo
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/datasheet.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/ddr3_interface_fast.csv
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/docs/phy_only_support_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/docs/ug586_7Series_MIS.pdf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/log.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/compatible_ucf/xc7k325tffg900_pkg.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/compatible_ucf/xc7k325tffg900_pkg.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/coregen.cgc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/coregen.cgp
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/create_ise.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.constraints/ddr_icon.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.constraints/ddr_icon.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon_cg.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_icon_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.constraints/ddr_ila_basic.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.constraints/ddr_ila_basic.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic_cg.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_basic_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.constraints/ddr_ila_rdpath.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.constraints/ddr_ila_rdpath.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath_cg.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_rdpath_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.constraints/ddr_ila_wrpath.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.constraints/ddr_ila_wrpath.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath_cg.xco
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_ila_wrpath_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.constraints/ddr_vio_async_in_sync_out.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.constraints/ddr_vio_async_in_sync_out.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out.xise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out_cg.xco
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_async_in_sync_out_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.asy
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.constraints/ddr_vio_sync_async_out72.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.constraints/ddr_vio_sync_async_out72.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.gise
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.ncf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72.xco
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ddr_vio_sync_async_out72_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.bgn
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.bit
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.bld
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.cdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.cpj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.drc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.ncd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.ngc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.ngd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.pad
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.par
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.pcf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.ptwx
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.syr
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.twr
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.twx
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.unroutes
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top.xdc
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top_bitgen.xwbt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top_map.map
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top_map.mrp
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top_map.ncd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top_map.ngm
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top_map.xrpt
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/example_top_xst.xrpt
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-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/ise_flow_results.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/makeproj.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/par_usage_statistics.html
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/rem_files.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/rem_files.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/set_ise_prop.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/vivado.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/vivado_gui.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/xlnx_auto_0_xdb/cst.xbcd
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/par/xst_options.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/ddr2_ddr3_chipscope.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/example_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_tg.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_data_gen_chk.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_tg.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/ddr3_model.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/ddr3_model_parameters.vh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/sim.do
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/sim_tb_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/wiredly.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/xsim_files.prj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/xsim_options.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/sim/xsim_run.sh
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/synth/_ngo/netlist.lst
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/synth/example_top.lso
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/example_design/synth/example_top.prj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/mig.prj
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/constraints/compatible_ucf/xc7k325tffg900_pkg.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/constraints/compatible_ucf/xc7k325tffg900_pkg.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/constraints/ddr3_interface_fast.ucf
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/constraints/ddr3_interface_fast.xdc
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/log.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_mux.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_common.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_col_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_common.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_mach.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_dec_fix.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_merge_enc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_top.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_fast_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen/ddr3_interface_xmdf.tcl
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-share/uhd/fpga/usrp3/top/x300/coregen/fifo_4k_2clk/implement/implement.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/fifo_4k_2clk/implement/planAhead_ise.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/implement/implement.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/functional/wave.do
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-share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/simulate_mti.bat
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-share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/wave.do
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-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint1COEFF_auto_HALFBAND_CENTRE0.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint1_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint1_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint1_reload_addrfilt_decode_rom.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint1_reload_order.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint1_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint1filt_decode_rom.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.asy
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.gise
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.ngc
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.v
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.veo
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.xco
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2.xise
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2COEFF_auto0_0.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2COEFF_auto0_1.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2COEFF_auto0_2.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2COEFF_auto_HALFBAND_CENTRE0.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2_reload_addrfilt_decode_rom.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2_reload_order.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint2filt_decode_rom.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.asy
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.gise
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.ngc
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.v
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.veo
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.xco
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3.xise
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3COEFF_auto0_0.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3COEFF_auto0_1.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3COEFF_auto0_2.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3COEFF_auto0_3.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3COEFF_auto0_4.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3COEFF_auto0_5.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3COEFF_auto_HALFBAND_CENTRE0.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3_flist.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3_readme.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3_reload_addrfilt_decode_rom.mif
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3_reload_order.txt
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3_xmdf.tcl
-share/uhd/fpga/usrp3/top/x300/coregen_dsp/hbint3filt_decode_rom.mif
-share/uhd/fpga/usrp3/top/x300/dbuf_bootram.v
-share/uhd/fpga/usrp3/top/x300/ddr3.ucf
-share/uhd/fpga/usrp3/top/x300/floorplan_X300.ucf
-share/uhd/fpga/usrp3/top/x300/floorplan_X310.ucf
-share/uhd/fpga/usrp3/top/x300/gen_ddrlvds.v
-share/uhd/fpga/usrp3/top/x300/gen_ddrlvds_tb.build
-share/uhd/fpga/usrp3/top/x300/gen_ddrlvds_tb.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/README
-share/uhd/fpga/usrp3/top/x300/gige_phy/gige_phy_mdio.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_block.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_reset_sync.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/gige_sfp_mdio_sync_block.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_transceiver.v
-share/uhd/fpga/usrp3/top/x300/gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v
-share/uhd/fpga/usrp3/top/x300/radio.v
-share/uhd/fpga/usrp3/top/x300/radio_tb.v
-share/uhd/fpga/usrp3/top/x300/sim/sim_dram_example_design/bootram.mif
-share/uhd/fpga/usrp3/top/x300/sim/sim_dram_example_design/files.prj
-share/uhd/fpga/usrp3/top/x300/sim/sim_dram_example_design/run_sim
-share/uhd/fpga/usrp3/top/x300/sim/sim_vfifo_tester/bootram.mif
-share/uhd/fpga/usrp3/top/x300/sim/sim_vfifo_tester/files.prj
-share/uhd/fpga/usrp3/top/x300/sim/sim_vfifo_tester/run_sim
-share/uhd/fpga/usrp3/top/x300/sim/x300_tb.v
-share/uhd/fpga/usrp3/top/x300/soft_ctrl.v
-share/uhd/fpga/usrp3/top/x300/stc3.ucf
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/README
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_block.v
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_mod.v
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf
-share/uhd/fpga/usrp3/top/x300/ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v
-share/uhd/fpga/usrp3/top/x300/timing.ucf
-share/uhd/fpga/usrp3/top/x300/x300.ucf
-share/uhd/fpga/usrp3/top/x300/x300.v
-share/uhd/fpga/usrp3/top/x300/x300_10ge.ucf
-share/uhd/fpga/usrp3/top/x300/x300_10ge_port0.ucf
-share/uhd/fpga/usrp3/top/x300/x300_10ge_port1.ucf
-share/uhd/fpga/usrp3/top/x300/x300_1ge.ucf
-share/uhd/fpga/usrp3/top/x300/x300_core.v
-share/uhd/fpga/usrp3/top/x300/x300_cpri.ucf
-share/uhd/fpga/usrp3/top/x300/x300_pcie_int.v
-share/uhd/fpga/usrp3/top/x300/x300_pcie_int_tb.v
-share/uhd/fpga/usrp3/top/x300/x300_zpu_config.vhd
-share/uhd/fpga/usrp3/top/x300/x3x0_base.lvbitx
-share/uhd/fpga/usrp3/vita_chdr.txt
-share/uhd/images/CMakeLists.txt
-share/uhd/images/Makefile
-share/uhd/images/README.md
diff --git a/uhd/PLIST.doxygen b/uhd/PLIST.doxygen
deleted file mode 100644
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--- a/uhd/PLIST.doxygen
+++ /dev/null
@@ -1,820 +0,0 @@
-share/doc/uhd/doxygen/html/algorithm_8hpp.html
-share/doc/uhd/doxygen/html/algorithm_8hpp_source.html
-share/doc/uhd/doxygen/html/annotated.html
-share/doc/uhd/doxygen/html/assert__has_8hpp.html
-share/doc/uhd/doxygen/html/assert__has_8hpp_source.html
-share/doc/uhd/doxygen/html/atomic_8hpp.html
-share/doc/uhd/doxygen/html/atomic_8hpp_source.html
-share/doc/uhd/doxygen/html/bc_s.png
-share/doc/uhd/doxygen/html/bdwn.png
-share/doc/uhd/doxygen/html/bounded__buffer_8hpp.html
-share/doc/uhd/doxygen/html/bounded__buffer_8hpp_source.html
-share/doc/uhd/doxygen/html/buffer__pool_8hpp.html
-share/doc/uhd/doxygen/html/buffer__pool_8hpp_source.html
-share/doc/uhd/doxygen/html/byteswap_8hpp.html
-share/doc/uhd/doxygen/html/byteswap_8hpp_source.html
-share/doc/uhd/doxygen/html/cast_8hpp.html
-share/doc/uhd/doxygen/html/cast_8hpp_source.html
-share/doc/uhd/doxygen/html/classes.html
-share/doc/uhd/doxygen/html/classuhd_1_1__log_1_1log-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1__log_1_1log.html
-share/doc/uhd/doxygen/html/classuhd_1_1atomic__uint32__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1atomic__uint32__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1convert_1_1converter-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1convert_1_1converter.html
-share/doc/uhd/doxygen/html/classuhd_1_1device-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1device.html
-share/doc/uhd/doxygen/html/classuhd_1_1device.png
-share/doc/uhd/doxygen/html/classuhd_1_1device__addr__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1device__addr__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1device__addr__t.png
-share/doc/uhd/doxygen/html/classuhd_1_1dict-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1dict.html
-share/doc/uhd/doxygen/html/classuhd_1_1gain__group-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1gain__group.html
-share/doc/uhd/doxygen/html/classuhd_1_1gain__group.png
-share/doc/uhd/doxygen/html/classuhd_1_1gps__ctrl-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1gps__ctrl.html
-share/doc/uhd/doxygen/html/classuhd_1_1gps__ctrl.png
-share/doc/uhd/doxygen/html/classuhd_1_1i2c__iface-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1i2c__iface.html
-share/doc/uhd/doxygen/html/classuhd_1_1i2c__iface.png
-share/doc/uhd/doxygen/html/classuhd_1_1io__type__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1io__type__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1mac__addr__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1mac__addr__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1msg_1_1__msg-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1msg_1_1__msg.html
-share/doc/uhd/doxygen/html/classuhd_1_1msg__task-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1msg__task.html
-share/doc/uhd/doxygen/html/classuhd_1_1msg__task.png
-share/doc/uhd/doxygen/html/classuhd_1_1property-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1property.html
-share/doc/uhd/doxygen/html/classuhd_1_1property.png
-share/doc/uhd/doxygen/html/classuhd_1_1property__tree-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1property__tree.html
-share/doc/uhd/doxygen/html/classuhd_1_1property__tree.png
-share/doc/uhd/doxygen/html/classuhd_1_1range__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1range__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1ref__vector-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1ref__vector.html
-share/doc/uhd/doxygen/html/classuhd_1_1reusable__barrier-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1reusable__barrier.html
-share/doc/uhd/doxygen/html/classuhd_1_1rx__streamer-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1rx__streamer.html
-share/doc/uhd/doxygen/html/classuhd_1_1rx__streamer.png
-share/doc/uhd/doxygen/html/classuhd_1_1simple__claimer-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1simple__claimer.html
-share/doc/uhd/doxygen/html/classuhd_1_1spi__iface-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1spi__iface.html
-share/doc/uhd/doxygen/html/classuhd_1_1task-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1task.html
-share/doc/uhd/doxygen/html/classuhd_1_1task.png
-share/doc/uhd/doxygen/html/classuhd_1_1time__spec__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1time__spec__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1time__spec__t.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1bounded__buffer-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1bounded__buffer.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1buffer__pool-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1buffer__pool.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1buffer__pool.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__buffer-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__buffer.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__buffer.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__recv__buffer-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__recv__buffer.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__recv__buffer.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__send__buffer-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__send__buffer.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1managed__send__buffer.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1nirio__zero__copy-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1nirio__zero__copy.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1nirio__zero__copy.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1udp__simple-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1udp__simple.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1udp__simple.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1udp__zero__copy-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1udp__zero__copy.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1udp__zero__copy.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__control-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__control.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__control.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__device__handle-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__device__handle.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__device__handle.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__zero__copy-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__zero__copy.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1usb__zero__copy.png
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1zero__copy__if-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1zero__copy__if.html
-share/doc/uhd/doxygen/html/classuhd_1_1transport_1_1zero__copy__if.png
-share/doc/uhd/doxygen/html/classuhd_1_1tx__streamer-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1tx__streamer.html
-share/doc/uhd/doxygen/html/classuhd_1_1tx__streamer.png
-share/doc/uhd/doxygen/html/classuhd_1_1uart__iface-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1uart__iface.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__base-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__base.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__base.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__id__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__id__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__id__t.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__iface-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__iface.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__iface.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__manager-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__manager.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1dboard__manager.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1multi__usrp-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1rx__dboard__base-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1rx__dboard__base.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1rx__dboard__base.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1subdev__spec__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1subdev__spec__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1subdev__spec__t.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1tx__dboard__base-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1tx__dboard__base.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1tx__dboard__base.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1xcvr__dboard__base-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1xcvr__dboard__base.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrp_1_1xcvr__dboard__base.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1boost__serialization__archive__utils-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1boost__serialization__archive__utils.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__args__header__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__args__header__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__args__reader__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__args__reader__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__args__writer__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__args__writer__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__xport__buf__t-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1func__xport__buf__t.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1rpc__client-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1rpc__client.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1rpc__client.png
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1usrprio__rpc__client-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1usrprio__rpc_1_1usrprio__rpc__client.html
-share/doc/uhd/doxygen/html/classuhd_1_1wb__iface-members.html
-share/doc/uhd/doxygen/html/classuhd_1_1wb__iface.html
-share/doc/uhd/doxygen/html/clock__config_8hpp.html
-share/doc/uhd/doxygen/html/clock__config_8hpp_source.html
-share/doc/uhd/doxygen/html/closed.png
-share/doc/uhd/doxygen/html/config_8hpp.html
-share/doc/uhd/doxygen/html/config_8hpp_source.html
-share/doc/uhd/doxygen/html/convert_8hpp.html
-share/doc/uhd/doxygen/html/convert_8hpp_source.html
-share/doc/uhd/doxygen/html/csv_8hpp.html
-share/doc/uhd/doxygen/html/csv_8hpp_source.html
-share/doc/uhd/doxygen/html/dboard__base_8hpp.html
-share/doc/uhd/doxygen/html/dboard__base_8hpp_source.html
-share/doc/uhd/doxygen/html/dboard__eeprom_8hpp.html
-share/doc/uhd/doxygen/html/dboard__eeprom_8hpp_source.html
-share/doc/uhd/doxygen/html/dboard__id_8hpp.html
-share/doc/uhd/doxygen/html/dboard__id_8hpp_source.html
-share/doc/uhd/doxygen/html/dboard__iface_8hpp.html
-share/doc/uhd/doxygen/html/dboard__iface_8hpp_source.html
-share/doc/uhd/doxygen/html/dboard__manager_8hpp.html
-share/doc/uhd/doxygen/html/dboard__manager_8hpp_source.html
-share/doc/uhd/doxygen/html/deprecated_8hpp.html
-share/doc/uhd/doxygen/html/deprecated_8hpp_source.html
-share/doc/uhd/doxygen/html/device_8hpp.html
-share/doc/uhd/doxygen/html/device_8hpp_source.html
-share/doc/uhd/doxygen/html/device__addr_8hpp.html
-share/doc/uhd/doxygen/html/device__addr_8hpp_source.html
-share/doc/uhd/doxygen/html/dict_8hpp.html
-share/doc/uhd/doxygen/html/dict_8hpp_source.html
-share/doc/uhd/doxygen/html/dir_000000.html
-share/doc/uhd/doxygen/html/dir_000001.html
-share/doc/uhd/doxygen/html/dir_000002.html
-share/doc/uhd/doxygen/html/dir_000003.html
-share/doc/uhd/doxygen/html/dir_000004.html
-share/doc/uhd/doxygen/html/dir_000005.html
-share/doc/uhd/doxygen/html/dir_000006.html
-share/doc/uhd/doxygen/html/dir_000007.html
-share/doc/uhd/doxygen/html/doxygen.css
-share/doc/uhd/doxygen/html/doxygen.png
-share/doc/uhd/doxygen/html/dynsections.js
-share/doc/uhd/doxygen/html/exception_8hpp.html
-share/doc/uhd/doxygen/html/exception_8hpp_source.html
-share/doc/uhd/doxygen/html/files.html
-share/doc/uhd/doxygen/html/ftv2blank.png
-share/doc/uhd/doxygen/html/ftv2doc.png
-share/doc/uhd/doxygen/html/ftv2folderclosed.png
-share/doc/uhd/doxygen/html/ftv2folderopen.png
-share/doc/uhd/doxygen/html/ftv2lastnode.png
-share/doc/uhd/doxygen/html/ftv2link.png
-share/doc/uhd/doxygen/html/ftv2mlastnode.png
-share/doc/uhd/doxygen/html/ftv2mnode.png
-share/doc/uhd/doxygen/html/ftv2node.png
-share/doc/uhd/doxygen/html/ftv2plastnode.png
-share/doc/uhd/doxygen/html/ftv2pnode.png
-share/doc/uhd/doxygen/html/ftv2splitbar.png
-share/doc/uhd/doxygen/html/ftv2vertline.png
-share/doc/uhd/doxygen/html/functions.html
-share/doc/uhd/doxygen/html/functions_a.html
-share/doc/uhd/doxygen/html/functions_b.html
-share/doc/uhd/doxygen/html/functions_c.html
-share/doc/uhd/doxygen/html/functions_d.html
-share/doc/uhd/doxygen/html/functions_e.html
-share/doc/uhd/doxygen/html/functions_enum.html
-share/doc/uhd/doxygen/html/functions_eval.html
-share/doc/uhd/doxygen/html/functions_f.html
-share/doc/uhd/doxygen/html/functions_func.html
-share/doc/uhd/doxygen/html/functions_func_a.html
-share/doc/uhd/doxygen/html/functions_func_b.html
-share/doc/uhd/doxygen/html/functions_func_c.html
-share/doc/uhd/doxygen/html/functions_func_d.html
-share/doc/uhd/doxygen/html/functions_func_e.html
-share/doc/uhd/doxygen/html/functions_func_f.html
-share/doc/uhd/doxygen/html/functions_func_g.html
-share/doc/uhd/doxygen/html/functions_func_h.html
-share/doc/uhd/doxygen/html/functions_func_i.html
-share/doc/uhd/doxygen/html/functions_func_k.html
-share/doc/uhd/doxygen/html/functions_func_l.html
-share/doc/uhd/doxygen/html/functions_func_m.html
-share/doc/uhd/doxygen/html/functions_func_n.html
-share/doc/uhd/doxygen/html/functions_func_o.html
-share/doc/uhd/doxygen/html/functions_func_p.html
-share/doc/uhd/doxygen/html/functions_func_r.html
-share/doc/uhd/doxygen/html/functions_func_s.html
-share/doc/uhd/doxygen/html/functions_func_t.html
-share/doc/uhd/doxygen/html/functions_func_u.html
-share/doc/uhd/doxygen/html/functions_func_v.html
-share/doc/uhd/doxygen/html/functions_func_w.html
-share/doc/uhd/doxygen/html/functions_func_x.html
-share/doc/uhd/doxygen/html/functions_func_~.html
-share/doc/uhd/doxygen/html/functions_g.html
-share/doc/uhd/doxygen/html/functions_h.html
-share/doc/uhd/doxygen/html/functions_i.html
-share/doc/uhd/doxygen/html/functions_k.html
-share/doc/uhd/doxygen/html/functions_l.html
-share/doc/uhd/doxygen/html/functions_m.html
-share/doc/uhd/doxygen/html/functions_n.html
-share/doc/uhd/doxygen/html/functions_o.html
-share/doc/uhd/doxygen/html/functions_p.html
-share/doc/uhd/doxygen/html/functions_r.html
-share/doc/uhd/doxygen/html/functions_s.html
-share/doc/uhd/doxygen/html/functions_t.html
-share/doc/uhd/doxygen/html/functions_type.html
-share/doc/uhd/doxygen/html/functions_u.html
-share/doc/uhd/doxygen/html/functions_v.html
-share/doc/uhd/doxygen/html/functions_vars.html
-share/doc/uhd/doxygen/html/functions_w.html
-share/doc/uhd/doxygen/html/functions_x.html
-share/doc/uhd/doxygen/html/functions_~.html
-share/doc/uhd/doxygen/html/gain__group_8hpp.html
-share/doc/uhd/doxygen/html/gain__group_8hpp_source.html
-share/doc/uhd/doxygen/html/globals.html
-share/doc/uhd/doxygen/html/globals_defs.html
-share/doc/uhd/doxygen/html/gps__ctrl_8hpp.html
-share/doc/uhd/doxygen/html/gps__ctrl_8hpp_source.html
-share/doc/uhd/doxygen/html/hierarchy.html
-share/doc/uhd/doxygen/html/if__addrs_8hpp.html
-share/doc/uhd/doxygen/html/if__addrs_8hpp_source.html
-share/doc/uhd/doxygen/html/images_8hpp.html
-share/doc/uhd/doxygen/html/images_8hpp_source.html
-share/doc/uhd/doxygen/html/index.html
-share/doc/uhd/doxygen/html/io__type_8hpp.html
-share/doc/uhd/doxygen/html/io__type_8hpp_source.html
-share/doc/uhd/doxygen/html/jquery.js
-share/doc/uhd/doxygen/html/log_8hpp.html
-share/doc/uhd/doxygen/html/log_8hpp_source.html
-share/doc/uhd/doxygen/html/mac__addr_8hpp.html
-share/doc/uhd/doxygen/html/mac__addr_8hpp_source.html
-share/doc/uhd/doxygen/html/mboard__eeprom_8hpp.html
-share/doc/uhd/doxygen/html/mboard__eeprom_8hpp_source.html
-share/doc/uhd/doxygen/html/metadata_8hpp.html
-share/doc/uhd/doxygen/html/metadata_8hpp_source.html
-share/doc/uhd/doxygen/html/msg_8hpp.html
-share/doc/uhd/doxygen/html/msg_8hpp_source.html
-share/doc/uhd/doxygen/html/msg__task_8hpp.html
-share/doc/uhd/doxygen/html/msg__task_8hpp_source.html
-share/doc/uhd/doxygen/html/multi__usrp_8hpp.html
-share/doc/uhd/doxygen/html/multi__usrp_8hpp_source.html
-share/doc/uhd/doxygen/html/namespacemembers.html
-share/doc/uhd/doxygen/html/namespacemembers_enum.html
-share/doc/uhd/doxygen/html/namespacemembers_eval.html
-share/doc/uhd/doxygen/html/namespacemembers_func.html
-share/doc/uhd/doxygen/html/namespacemembers_type.html
-share/doc/uhd/doxygen/html/namespaces.html
-share/doc/uhd/doxygen/html/namespaceuhd.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1__log.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1cast.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1convert.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1csv.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1msg.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1transport.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1transport_1_1vrt.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1usrp.html
-share/doc/uhd/doxygen/html/namespaceuhd_1_1usrprio__rpc.html
-share/doc/uhd/doxygen/html/nav_f.png
-share/doc/uhd/doxygen/html/nav_g.png
-share/doc/uhd/doxygen/html/nav_h.png
-share/doc/uhd/doxygen/html/nirio__zero__copy_8hpp.html
-share/doc/uhd/doxygen/html/nirio__zero__copy_8hpp_source.html
-share/doc/uhd/doxygen/html/open.png
-share/doc/uhd/doxygen/html/otw__type_8hpp.html
-share/doc/uhd/doxygen/html/otw__type_8hpp_source.html
-share/doc/uhd/doxygen/html/paths_8hpp.html
-share/doc/uhd/doxygen/html/paths_8hpp_source.html
-share/doc/uhd/doxygen/html/pimpl_8hpp.html
-share/doc/uhd/doxygen/html/pimpl_8hpp_source.html
-share/doc/uhd/doxygen/html/platform_8hpp.html
-share/doc/uhd/doxygen/html/platform_8hpp_source.html
-share/doc/uhd/doxygen/html/property__tree_8hpp.html
-share/doc/uhd/doxygen/html/property__tree_8hpp_source.html
-share/doc/uhd/doxygen/html/ranges_8hpp.html
-share/doc/uhd/doxygen/html/ranges_8hpp_source.html
-share/doc/uhd/doxygen/html/ref__vector_8hpp.html
-share/doc/uhd/doxygen/html/ref__vector_8hpp_source.html
-share/doc/uhd/doxygen/html/rpc__client_8hpp.html
-share/doc/uhd/doxygen/html/rpc__client_8hpp_source.html
-share/doc/uhd/doxygen/html/rpc__common_8hpp.html
-share/doc/uhd/doxygen/html/rpc__common_8hpp_source.html
-share/doc/uhd/doxygen/html/safe__call_8hpp.html
-share/doc/uhd/doxygen/html/safe__call_8hpp_source.html
-share/doc/uhd/doxygen/html/safe__main_8hpp.html
-share/doc/uhd/doxygen/html/safe__main_8hpp_source.html
-share/doc/uhd/doxygen/html/search/all_0.html
-share/doc/uhd/doxygen/html/search/all_0.js
-share/doc/uhd/doxygen/html/search/all_1.html
-share/doc/uhd/doxygen/html/search/all_1.js
-share/doc/uhd/doxygen/html/search/all_10.html
-share/doc/uhd/doxygen/html/search/all_10.js
-share/doc/uhd/doxygen/html/search/all_11.html
-share/doc/uhd/doxygen/html/search/all_11.js
-share/doc/uhd/doxygen/html/search/all_12.html
-share/doc/uhd/doxygen/html/search/all_12.js
-share/doc/uhd/doxygen/html/search/all_13.html
-share/doc/uhd/doxygen/html/search/all_13.js
-share/doc/uhd/doxygen/html/search/all_14.html
-share/doc/uhd/doxygen/html/search/all_14.js
-share/doc/uhd/doxygen/html/search/all_15.html
-share/doc/uhd/doxygen/html/search/all_15.js
-share/doc/uhd/doxygen/html/search/all_16.html
-share/doc/uhd/doxygen/html/search/all_16.js
-share/doc/uhd/doxygen/html/search/all_17.html
-share/doc/uhd/doxygen/html/search/all_17.js
-share/doc/uhd/doxygen/html/search/all_18.html
-share/doc/uhd/doxygen/html/search/all_18.js
-share/doc/uhd/doxygen/html/search/all_2.html
-share/doc/uhd/doxygen/html/search/all_2.js
-share/doc/uhd/doxygen/html/search/all_3.html
-share/doc/uhd/doxygen/html/search/all_3.js
-share/doc/uhd/doxygen/html/search/all_4.html
-share/doc/uhd/doxygen/html/search/all_4.js
-share/doc/uhd/doxygen/html/search/all_5.html
-share/doc/uhd/doxygen/html/search/all_5.js
-share/doc/uhd/doxygen/html/search/all_6.html
-share/doc/uhd/doxygen/html/search/all_6.js
-share/doc/uhd/doxygen/html/search/all_7.html
-share/doc/uhd/doxygen/html/search/all_7.js
-share/doc/uhd/doxygen/html/search/all_8.html
-share/doc/uhd/doxygen/html/search/all_8.js
-share/doc/uhd/doxygen/html/search/all_9.html
-share/doc/uhd/doxygen/html/search/all_9.js
-share/doc/uhd/doxygen/html/search/all_a.html
-share/doc/uhd/doxygen/html/search/all_a.js
-share/doc/uhd/doxygen/html/search/all_b.html
-share/doc/uhd/doxygen/html/search/all_b.js
-share/doc/uhd/doxygen/html/search/all_c.html
-share/doc/uhd/doxygen/html/search/all_c.js
-share/doc/uhd/doxygen/html/search/all_d.html
-share/doc/uhd/doxygen/html/search/all_d.js
-share/doc/uhd/doxygen/html/search/all_e.html
-share/doc/uhd/doxygen/html/search/all_e.js
-share/doc/uhd/doxygen/html/search/all_f.html
-share/doc/uhd/doxygen/html/search/all_f.js
-share/doc/uhd/doxygen/html/search/classes_0.html
-share/doc/uhd/doxygen/html/search/classes_0.js
-share/doc/uhd/doxygen/html/search/classes_1.html
-share/doc/uhd/doxygen/html/search/classes_1.js
-share/doc/uhd/doxygen/html/search/classes_10.html
-share/doc/uhd/doxygen/html/search/classes_10.js
-share/doc/uhd/doxygen/html/search/classes_11.html
-share/doc/uhd/doxygen/html/search/classes_11.js
-share/doc/uhd/doxygen/html/search/classes_12.html
-share/doc/uhd/doxygen/html/search/classes_12.js
-share/doc/uhd/doxygen/html/search/classes_13.html
-share/doc/uhd/doxygen/html/search/classes_13.js
-share/doc/uhd/doxygen/html/search/classes_14.html
-share/doc/uhd/doxygen/html/search/classes_14.js
-share/doc/uhd/doxygen/html/search/classes_15.html
-share/doc/uhd/doxygen/html/search/classes_15.js
-share/doc/uhd/doxygen/html/search/classes_16.html
-share/doc/uhd/doxygen/html/search/classes_16.js
-share/doc/uhd/doxygen/html/search/classes_17.html
-share/doc/uhd/doxygen/html/search/classes_17.js
-share/doc/uhd/doxygen/html/search/classes_2.html
-share/doc/uhd/doxygen/html/search/classes_2.js
-share/doc/uhd/doxygen/html/search/classes_3.html
-share/doc/uhd/doxygen/html/search/classes_3.js
-share/doc/uhd/doxygen/html/search/classes_4.html
-share/doc/uhd/doxygen/html/search/classes_4.js
-share/doc/uhd/doxygen/html/search/classes_5.html
-share/doc/uhd/doxygen/html/search/classes_5.js
-share/doc/uhd/doxygen/html/search/classes_6.html
-share/doc/uhd/doxygen/html/search/classes_6.js
-share/doc/uhd/doxygen/html/search/classes_7.html
-share/doc/uhd/doxygen/html/search/classes_7.js
-share/doc/uhd/doxygen/html/search/classes_8.html
-share/doc/uhd/doxygen/html/search/classes_8.js
-share/doc/uhd/doxygen/html/search/classes_9.html
-share/doc/uhd/doxygen/html/search/classes_9.js
-share/doc/uhd/doxygen/html/search/classes_a.html
-share/doc/uhd/doxygen/html/search/classes_a.js
-share/doc/uhd/doxygen/html/search/classes_b.html
-share/doc/uhd/doxygen/html/search/classes_b.js
-share/doc/uhd/doxygen/html/search/classes_c.html
-share/doc/uhd/doxygen/html/search/classes_c.js
-share/doc/uhd/doxygen/html/search/classes_d.html
-share/doc/uhd/doxygen/html/search/classes_d.js
-share/doc/uhd/doxygen/html/search/classes_e.html
-share/doc/uhd/doxygen/html/search/classes_e.js
-share/doc/uhd/doxygen/html/search/classes_f.html
-share/doc/uhd/doxygen/html/search/classes_f.js
-share/doc/uhd/doxygen/html/search/close.png
-share/doc/uhd/doxygen/html/search/defines_0.html
-share/doc/uhd/doxygen/html/search/defines_0.js
-share/doc/uhd/doxygen/html/search/defines_1.html
-share/doc/uhd/doxygen/html/search/defines_1.js
-share/doc/uhd/doxygen/html/search/defines_2.html
-share/doc/uhd/doxygen/html/search/defines_2.js
-share/doc/uhd/doxygen/html/search/defines_3.html
-share/doc/uhd/doxygen/html/search/defines_3.js
-share/doc/uhd/doxygen/html/search/defines_4.html
-share/doc/uhd/doxygen/html/search/defines_4.js
-share/doc/uhd/doxygen/html/search/defines_5.html
-share/doc/uhd/doxygen/html/search/defines_5.js
-share/doc/uhd/doxygen/html/search/enums_0.html
-share/doc/uhd/doxygen/html/search/enums_0.js
-share/doc/uhd/doxygen/html/search/enums_1.html
-share/doc/uhd/doxygen/html/search/enums_1.js
-share/doc/uhd/doxygen/html/search/enums_2.html
-share/doc/uhd/doxygen/html/search/enums_2.js
-share/doc/uhd/doxygen/html/search/enums_3.html
-share/doc/uhd/doxygen/html/search/enums_3.js
-share/doc/uhd/doxygen/html/search/enums_4.html
-share/doc/uhd/doxygen/html/search/enums_4.js
-share/doc/uhd/doxygen/html/search/enums_5.html
-share/doc/uhd/doxygen/html/search/enums_5.js
-share/doc/uhd/doxygen/html/search/enums_6.html
-share/doc/uhd/doxygen/html/search/enums_6.js
-share/doc/uhd/doxygen/html/search/enums_7.html
-share/doc/uhd/doxygen/html/search/enums_7.js
-share/doc/uhd/doxygen/html/search/enums_8.html
-share/doc/uhd/doxygen/html/search/enums_8.js
-share/doc/uhd/doxygen/html/search/enums_9.html
-share/doc/uhd/doxygen/html/search/enums_9.js
-share/doc/uhd/doxygen/html/search/enumvalues_0.html
-share/doc/uhd/doxygen/html/search/enumvalues_0.js
-share/doc/uhd/doxygen/html/search/enumvalues_1.html
-share/doc/uhd/doxygen/html/search/enumvalues_1.js
-share/doc/uhd/doxygen/html/search/enumvalues_2.html
-share/doc/uhd/doxygen/html/search/enumvalues_2.js
-share/doc/uhd/doxygen/html/search/enumvalues_3.html
-share/doc/uhd/doxygen/html/search/enumvalues_3.js
-share/doc/uhd/doxygen/html/search/enumvalues_4.html
-share/doc/uhd/doxygen/html/search/enumvalues_4.js
-share/doc/uhd/doxygen/html/search/enumvalues_5.html
-share/doc/uhd/doxygen/html/search/enumvalues_5.js
-share/doc/uhd/doxygen/html/search/enumvalues_6.html
-share/doc/uhd/doxygen/html/search/enumvalues_6.js
-share/doc/uhd/doxygen/html/search/enumvalues_7.html
-share/doc/uhd/doxygen/html/search/enumvalues_7.js
-share/doc/uhd/doxygen/html/search/enumvalues_8.html
-share/doc/uhd/doxygen/html/search/enumvalues_8.js
-share/doc/uhd/doxygen/html/search/enumvalues_9.html
-share/doc/uhd/doxygen/html/search/enumvalues_9.js
-share/doc/uhd/doxygen/html/search/enumvalues_a.html
-share/doc/uhd/doxygen/html/search/enumvalues_a.js
-share/doc/uhd/doxygen/html/search/enumvalues_b.html
-share/doc/uhd/doxygen/html/search/enumvalues_b.js
-share/doc/uhd/doxygen/html/search/enumvalues_c.html
-share/doc/uhd/doxygen/html/search/enumvalues_c.js
-share/doc/uhd/doxygen/html/search/enumvalues_d.html
-share/doc/uhd/doxygen/html/search/enumvalues_d.js
-share/doc/uhd/doxygen/html/search/enumvalues_e.html
-share/doc/uhd/doxygen/html/search/enumvalues_e.js
-share/doc/uhd/doxygen/html/search/files_0.html
-share/doc/uhd/doxygen/html/search/files_0.js
-share/doc/uhd/doxygen/html/search/files_1.html
-share/doc/uhd/doxygen/html/search/files_1.js
-share/doc/uhd/doxygen/html/search/files_10.html
-share/doc/uhd/doxygen/html/search/files_10.js
-share/doc/uhd/doxygen/html/search/files_11.html
-share/doc/uhd/doxygen/html/search/files_11.js
-share/doc/uhd/doxygen/html/search/files_12.html
-share/doc/uhd/doxygen/html/search/files_12.js
-share/doc/uhd/doxygen/html/search/files_2.html
-share/doc/uhd/doxygen/html/search/files_2.js
-share/doc/uhd/doxygen/html/search/files_3.html
-share/doc/uhd/doxygen/html/search/files_3.js
-share/doc/uhd/doxygen/html/search/files_4.html
-share/doc/uhd/doxygen/html/search/files_4.js
-share/doc/uhd/doxygen/html/search/files_5.html
-share/doc/uhd/doxygen/html/search/files_5.js
-share/doc/uhd/doxygen/html/search/files_6.html
-share/doc/uhd/doxygen/html/search/files_6.js
-share/doc/uhd/doxygen/html/search/files_7.html
-share/doc/uhd/doxygen/html/search/files_7.js
-share/doc/uhd/doxygen/html/search/files_8.html
-share/doc/uhd/doxygen/html/search/files_8.js
-share/doc/uhd/doxygen/html/search/files_9.html
-share/doc/uhd/doxygen/html/search/files_9.js
-share/doc/uhd/doxygen/html/search/files_a.html
-share/doc/uhd/doxygen/html/search/files_a.js
-share/doc/uhd/doxygen/html/search/files_b.html
-share/doc/uhd/doxygen/html/search/files_b.js
-share/doc/uhd/doxygen/html/search/files_c.html
-share/doc/uhd/doxygen/html/search/files_c.js
-share/doc/uhd/doxygen/html/search/files_d.html
-share/doc/uhd/doxygen/html/search/files_d.js
-share/doc/uhd/doxygen/html/search/files_e.html
-share/doc/uhd/doxygen/html/search/files_e.js
-share/doc/uhd/doxygen/html/search/files_f.html
-share/doc/uhd/doxygen/html/search/files_f.js
-share/doc/uhd/doxygen/html/search/functions_0.html
-share/doc/uhd/doxygen/html/search/functions_0.js
-share/doc/uhd/doxygen/html/search/functions_1.html
-share/doc/uhd/doxygen/html/search/functions_1.js
-share/doc/uhd/doxygen/html/search/functions_10.html
-share/doc/uhd/doxygen/html/search/functions_10.js
-share/doc/uhd/doxygen/html/search/functions_11.html
-share/doc/uhd/doxygen/html/search/functions_11.js
-share/doc/uhd/doxygen/html/search/functions_12.html
-share/doc/uhd/doxygen/html/search/functions_12.js
-share/doc/uhd/doxygen/html/search/functions_13.html
-share/doc/uhd/doxygen/html/search/functions_13.js
-share/doc/uhd/doxygen/html/search/functions_14.html
-share/doc/uhd/doxygen/html/search/functions_14.js
-share/doc/uhd/doxygen/html/search/functions_15.html
-share/doc/uhd/doxygen/html/search/functions_15.js
-share/doc/uhd/doxygen/html/search/functions_16.html
-share/doc/uhd/doxygen/html/search/functions_16.js
-share/doc/uhd/doxygen/html/search/functions_17.html
-share/doc/uhd/doxygen/html/search/functions_17.js
-share/doc/uhd/doxygen/html/search/functions_2.html
-share/doc/uhd/doxygen/html/search/functions_2.js
-share/doc/uhd/doxygen/html/search/functions_3.html
-share/doc/uhd/doxygen/html/search/functions_3.js
-share/doc/uhd/doxygen/html/search/functions_4.html
-share/doc/uhd/doxygen/html/search/functions_4.js
-share/doc/uhd/doxygen/html/search/functions_5.html
-share/doc/uhd/doxygen/html/search/functions_5.js
-share/doc/uhd/doxygen/html/search/functions_6.html
-share/doc/uhd/doxygen/html/search/functions_6.js
-share/doc/uhd/doxygen/html/search/functions_7.html
-share/doc/uhd/doxygen/html/search/functions_7.js
-share/doc/uhd/doxygen/html/search/functions_8.html
-share/doc/uhd/doxygen/html/search/functions_8.js
-share/doc/uhd/doxygen/html/search/functions_9.html
-share/doc/uhd/doxygen/html/search/functions_9.js
-share/doc/uhd/doxygen/html/search/functions_a.html
-share/doc/uhd/doxygen/html/search/functions_a.js
-share/doc/uhd/doxygen/html/search/functions_b.html
-share/doc/uhd/doxygen/html/search/functions_b.js
-share/doc/uhd/doxygen/html/search/functions_c.html
-share/doc/uhd/doxygen/html/search/functions_c.js
-share/doc/uhd/doxygen/html/search/functions_d.html
-share/doc/uhd/doxygen/html/search/functions_d.js
-share/doc/uhd/doxygen/html/search/functions_e.html
-share/doc/uhd/doxygen/html/search/functions_e.js
-share/doc/uhd/doxygen/html/search/functions_f.html
-share/doc/uhd/doxygen/html/search/functions_f.js
-share/doc/uhd/doxygen/html/search/mag_sel.png
-share/doc/uhd/doxygen/html/search/namespaces_0.html
-share/doc/uhd/doxygen/html/search/namespaces_0.js
-share/doc/uhd/doxygen/html/search/nomatches.html
-share/doc/uhd/doxygen/html/search/search.css
-share/doc/uhd/doxygen/html/search/search.js
-share/doc/uhd/doxygen/html/search/search_l.png
-share/doc/uhd/doxygen/html/search/search_m.png
-share/doc/uhd/doxygen/html/search/search_r.png
-share/doc/uhd/doxygen/html/search/typedefs_0.html
-share/doc/uhd/doxygen/html/search/typedefs_0.js
-share/doc/uhd/doxygen/html/search/typedefs_1.html
-share/doc/uhd/doxygen/html/search/typedefs_1.js
-share/doc/uhd/doxygen/html/search/typedefs_2.html
-share/doc/uhd/doxygen/html/search/typedefs_2.js
-share/doc/uhd/doxygen/html/search/typedefs_3.html
-share/doc/uhd/doxygen/html/search/typedefs_3.js
-share/doc/uhd/doxygen/html/search/typedefs_4.html
-share/doc/uhd/doxygen/html/search/typedefs_4.js
-share/doc/uhd/doxygen/html/search/typedefs_5.html
-share/doc/uhd/doxygen/html/search/typedefs_5.js
-share/doc/uhd/doxygen/html/search/typedefs_6.html
-share/doc/uhd/doxygen/html/search/typedefs_6.js
-share/doc/uhd/doxygen/html/search/typedefs_7.html
-share/doc/uhd/doxygen/html/search/typedefs_7.js
-share/doc/uhd/doxygen/html/search/typedefs_8.html
-share/doc/uhd/doxygen/html/search/typedefs_8.js
-share/doc/uhd/doxygen/html/search/typedefs_9.html
-share/doc/uhd/doxygen/html/search/typedefs_9.js
-share/doc/uhd/doxygen/html/search/typedefs_a.html
-share/doc/uhd/doxygen/html/search/typedefs_a.js
-share/doc/uhd/doxygen/html/search/typedefs_b.html
-share/doc/uhd/doxygen/html/search/typedefs_b.js
-share/doc/uhd/doxygen/html/search/typedefs_c.html
-share/doc/uhd/doxygen/html/search/typedefs_c.js
-share/doc/uhd/doxygen/html/search/typedefs_d.html
-share/doc/uhd/doxygen/html/search/typedefs_d.js
-share/doc/uhd/doxygen/html/search/typedefs_e.html
-share/doc/uhd/doxygen/html/search/typedefs_e.js
-share/doc/uhd/doxygen/html/search/variables_0.html
-share/doc/uhd/doxygen/html/search/variables_0.js
-share/doc/uhd/doxygen/html/search/variables_1.html
-share/doc/uhd/doxygen/html/search/variables_1.js
-share/doc/uhd/doxygen/html/search/variables_10.html
-share/doc/uhd/doxygen/html/search/variables_10.js
-share/doc/uhd/doxygen/html/search/variables_11.html
-share/doc/uhd/doxygen/html/search/variables_11.js
-share/doc/uhd/doxygen/html/search/variables_12.html
-share/doc/uhd/doxygen/html/search/variables_12.js
-share/doc/uhd/doxygen/html/search/variables_13.html
-share/doc/uhd/doxygen/html/search/variables_13.js
-share/doc/uhd/doxygen/html/search/variables_14.html
-share/doc/uhd/doxygen/html/search/variables_14.js
-share/doc/uhd/doxygen/html/search/variables_2.html
-share/doc/uhd/doxygen/html/search/variables_2.js
-share/doc/uhd/doxygen/html/search/variables_3.html
-share/doc/uhd/doxygen/html/search/variables_3.js
-share/doc/uhd/doxygen/html/search/variables_4.html
-share/doc/uhd/doxygen/html/search/variables_4.js
-share/doc/uhd/doxygen/html/search/variables_5.html
-share/doc/uhd/doxygen/html/search/variables_5.js
-share/doc/uhd/doxygen/html/search/variables_6.html
-share/doc/uhd/doxygen/html/search/variables_6.js
-share/doc/uhd/doxygen/html/search/variables_7.html
-share/doc/uhd/doxygen/html/search/variables_7.js
-share/doc/uhd/doxygen/html/search/variables_8.html
-share/doc/uhd/doxygen/html/search/variables_8.js
-share/doc/uhd/doxygen/html/search/variables_9.html
-share/doc/uhd/doxygen/html/search/variables_9.js
-share/doc/uhd/doxygen/html/search/variables_a.html
-share/doc/uhd/doxygen/html/search/variables_a.js
-share/doc/uhd/doxygen/html/search/variables_b.html
-share/doc/uhd/doxygen/html/search/variables_b.js
-share/doc/uhd/doxygen/html/search/variables_c.html
-share/doc/uhd/doxygen/html/search/variables_c.js
-share/doc/uhd/doxygen/html/search/variables_d.html
-share/doc/uhd/doxygen/html/search/variables_d.js
-share/doc/uhd/doxygen/html/search/variables_e.html
-share/doc/uhd/doxygen/html/search/variables_e.js
-share/doc/uhd/doxygen/html/search/variables_f.html
-share/doc/uhd/doxygen/html/search/variables_f.js
-share/doc/uhd/doxygen/html/sensors_8hpp.html
-share/doc/uhd/doxygen/html/sensors_8hpp_source.html
-share/doc/uhd/doxygen/html/serial_8hpp.html
-share/doc/uhd/doxygen/html/serial_8hpp_source.html
-share/doc/uhd/doxygen/html/static_8hpp.html
-share/doc/uhd/doxygen/html/static_8hpp_source.html
-share/doc/uhd/doxygen/html/stream_8hpp.html
-share/doc/uhd/doxygen/html/stream_8hpp_source.html
-share/doc/uhd/doxygen/html/stream__cmd_8hpp.html
-share/doc/uhd/doxygen/html/stream__cmd_8hpp_source.html
-share/doc/uhd/doxygen/html/struct__uhd__static__fixture-members.html
-share/doc/uhd/doxygen/html/struct__uhd__static__fixture.html
-share/doc/uhd/doxygen/html/structuhd_1_1assertion__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1assertion__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1assertion__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1async__metadata__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1async__metadata__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1clock__config__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1clock__config__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1convert_1_1id__type-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1convert_1_1id__type.html
-share/doc/uhd/doxygen/html/structuhd_1_1convert_1_1id__type.png
-share/doc/uhd/doxygen/html/structuhd_1_1environment__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1environment__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1environment__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1exception-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1exception.html
-share/doc/uhd/doxygen/html/structuhd_1_1exception.png
-share/doc/uhd/doxygen/html/structuhd_1_1fs__path-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1fs__path.html
-share/doc/uhd/doxygen/html/structuhd_1_1fs__path.png
-share/doc/uhd/doxygen/html/structuhd_1_1gain__fcns__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1gain__fcns__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1index__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1index__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1index__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1io__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1io__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1io__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1key__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1key__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1key__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1lookup__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1lookup__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1lookup__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1meta__range__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1meta__range__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1meta__range__t.png
-share/doc/uhd/doxygen/html/structuhd_1_1not__implemented__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1not__implemented__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1not__implemented__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1os__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1os__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1os__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1otw__type__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1otw__type__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1runtime__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1runtime__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1runtime__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1rx__metadata__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1rx__metadata__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1sensor__value__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1sensor__value__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1spi__config__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1spi__config__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1stream__args__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1stream__args__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1stream__cmd__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1stream__cmd__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1system__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1system__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1system__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1if__addrs__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1if__addrs__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1tcp__zero__copy-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1tcp__zero__copy.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1tcp__zero__copy.png
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1udp__zero__copy_1_1buff__params-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1udp__zero__copy_1_1buff__params.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1vrt_1_1if__packet__info__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1vrt_1_1if__packet__info__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1zero__copy__xport__params-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1transport_1_1zero__copy__xport__params.html
-share/doc/uhd/doxygen/html/structuhd_1_1tune__request__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1tune__request__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1tune__result__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1tune__result__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1tx__metadata__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1tx__metadata__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1type__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1type__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1type__error.png
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1dboard__eeprom__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1dboard__eeprom__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1dboard__iface__special__props__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1dboard__iface__special__props__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1mboard__eeprom__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1mboard__eeprom__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1mboard__eeprom__t.png
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1subdev__spec__pair__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1subdev__spec__pair__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrp_1_1subdev__spec__pair__t.png
-share/doc/uhd/doxygen/html/structuhd_1_1usrprio__rpc_1_1hshake__args__t-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrprio__rpc_1_1hshake__args__t.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrprio__rpc_1_1usrprio__device__info-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1usrprio__rpc_1_1usrprio__device__info.html
-share/doc/uhd/doxygen/html/structuhd_1_1value__error-members.html
-share/doc/uhd/doxygen/html/structuhd_1_1value__error.html
-share/doc/uhd/doxygen/html/structuhd_1_1value__error.png
-share/doc/uhd/doxygen/html/subdev__spec_8hpp.html
-share/doc/uhd/doxygen/html/subdev__spec_8hpp_source.html
-share/doc/uhd/doxygen/html/sync_off.png
-share/doc/uhd/doxygen/html/sync_on.png
-share/doc/uhd/doxygen/html/tab_a.png
-share/doc/uhd/doxygen/html/tab_b.png
-share/doc/uhd/doxygen/html/tab_h.png
-share/doc/uhd/doxygen/html/tab_s.png
-share/doc/uhd/doxygen/html/tabs.css
-share/doc/uhd/doxygen/html/tasks_8hpp.html
-share/doc/uhd/doxygen/html/tasks_8hpp_source.html
-share/doc/uhd/doxygen/html/tcp__zero__copy_8hpp.html
-share/doc/uhd/doxygen/html/tcp__zero__copy_8hpp_source.html
-share/doc/uhd/doxygen/html/thread__priority_8hpp.html
-share/doc/uhd/doxygen/html/thread__priority_8hpp_source.html
-share/doc/uhd/doxygen/html/time__spec_8hpp.html
-share/doc/uhd/doxygen/html/time__spec_8hpp_source.html
-share/doc/uhd/doxygen/html/tune__request_8hpp.html
-share/doc/uhd/doxygen/html/tune__request_8hpp_source.html
-share/doc/uhd/doxygen/html/tune__result_8hpp.html
-share/doc/uhd/doxygen/html/tune__result_8hpp_source.html
-share/doc/uhd/doxygen/html/udp__constants_8hpp.html
-share/doc/uhd/doxygen/html/udp__constants_8hpp_source.html
-share/doc/uhd/doxygen/html/udp__simple_8hpp.html
-share/doc/uhd/doxygen/html/udp__simple_8hpp_source.html
-share/doc/uhd/doxygen/html/udp__zero__copy_8hpp.html
-share/doc/uhd/doxygen/html/udp__zero__copy_8hpp_source.html
-share/doc/uhd/doxygen/html/usb__control_8hpp.html
-share/doc/uhd/doxygen/html/usb__control_8hpp_source.html
-share/doc/uhd/doxygen/html/usb__device__handle_8hpp.html
-share/doc/uhd/doxygen/html/usb__device__handle_8hpp_source.html
-share/doc/uhd/doxygen/html/usb__zero__copy_8hpp.html
-share/doc/uhd/doxygen/html/usb__zero__copy_8hpp_source.html
-share/doc/uhd/doxygen/html/usrprio__rpc__client_8hpp.html
-share/doc/uhd/doxygen/html/usrprio__rpc__client_8hpp_source.html
-share/doc/uhd/doxygen/html/usrprio__rpc__common_8hpp.html
-share/doc/uhd/doxygen/html/usrprio__rpc__common_8hpp_source.html
-share/doc/uhd/doxygen/html/version_8hpp.html
-share/doc/uhd/doxygen/html/version_8hpp_source.html
-share/doc/uhd/doxygen/html/vrt__if__packet_8hpp.html
-share/doc/uhd/doxygen/html/vrt__if__packet_8hpp_source.html
-share/doc/uhd/doxygen/html/wb__iface_8hpp.html
-share/doc/uhd/doxygen/html/wb__iface_8hpp_source.html
-share/doc/uhd/doxygen/html/zero__copy_8hpp.html
-share/doc/uhd/doxygen/html/zero__copy_8hpp_source.html
diff --git a/uhd/PLIST.manual b/uhd/PLIST.manual
deleted file mode 100644
index 02a7fd4..0000000
--- a/uhd/PLIST.manual
+++ /dev/null
@@ -1,48 +0,0 @@
-@comment $NetBSD: PLIST.manual,v 1.2 2014/09/08 04:29:33 makoto Exp $
-share/doc/uhd/manual/html/build.html
-share/doc/uhd/manual/html/calibration.html
-share/doc/uhd/manual/html/coding.html
-share/doc/uhd/manual/html/dboards.html
-share/doc/uhd/manual/html/general.html
-share/doc/uhd/manual/html/gpio_api.html
-share/doc/uhd/manual/html/gpsdo.html
-share/doc/uhd/manual/html/gpsdo_b2x0.html
-share/doc/uhd/manual/html/gpsdo_x3x0.html
-share/doc/uhd/manual/html/identification.html
-share/doc/uhd/manual/html/images.html
-share/doc/uhd/manual/html/index.html
-share/doc/uhd/manual/html/res/x3x0_fp_overlay.png
-share/doc/uhd/manual/html/res/x3x0_gpio_conn.png
-share/doc/uhd/manual/html/res/x3x0_rp_overlay.png
-share/doc/uhd/manual/html/stream.html
-share/doc/uhd/manual/html/sync.html
-share/doc/uhd/manual/html/transport.html
-share/doc/uhd/manual/html/usrp1.html
-share/doc/uhd/manual/html/usrp2.html
-share/doc/uhd/manual/html/usrp_b100.html
-share/doc/uhd/manual/html/usrp_b200.html
-share/doc/uhd/manual/html/usrp_e1x0.html
-share/doc/uhd/manual/html/usrp_x3x0.html
-share/doc/uhd/manual/html/usrp_x3x0_config.html
-share/doc/uhd/manual/rst/build.rst
-share/doc/uhd/manual/rst/calibration.rst
-share/doc/uhd/manual/rst/coding.rst
-share/doc/uhd/manual/rst/dboards.rst
-share/doc/uhd/manual/rst/general.rst
-share/doc/uhd/manual/rst/gpio_api.rst
-share/doc/uhd/manual/rst/gpsdo.rst
-share/doc/uhd/manual/rst/gpsdo_b2x0.rst
-share/doc/uhd/manual/rst/gpsdo_x3x0.rst
-share/doc/uhd/manual/rst/identification.rst
-share/doc/uhd/manual/rst/images.rst
-share/doc/uhd/manual/rst/index.rst
-share/doc/uhd/manual/rst/stream.rst
-share/doc/uhd/manual/rst/sync.rst
-share/doc/uhd/manual/rst/transport.rst
-share/doc/uhd/manual/rst/usrp1.rst
-share/doc/uhd/manual/rst/usrp2.rst
-share/doc/uhd/manual/rst/usrp_b100.rst
-share/doc/uhd/manual/rst/usrp_b200.rst
-share/doc/uhd/manual/rst/usrp_e1x0.rst
-share/doc/uhd/manual/rst/usrp_x3x0.rst
-share/doc/uhd/manual/rst/usrp_x3x0_config.rst
diff --git a/uhd/TODO b/uhd/TODO
deleted file mode 100644
index 5426870..0000000
--- a/uhd/TODO
+++ /dev/null
@@ -1,39 +0,0 @@
-- Not all arguments of CMAKE command line are reviewed (do-configure:)
-- Install path for firmware, fpga and image are not checked
- for being referenced from other packages
--(for commit log)
- [USRP-users] [UHD-3.7.2-rc1] Release Candidate Announcement
- http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2014-July/010219.html
-
-(build-ninja) problem:
-
-[293/293] Linking CXX executable utils/usrp_x3xx_fpga_burner
-FAILED: : &&
-/export/WRKOBJDIR/wip/uhd-git/work/.wrapper/bin/c++ -O2
--I/usr/include -I/usr/pkg/include -DNDEBUG -L/usr/lib
--Wl,-R/usr/lib -L/usr/pkg/lib -Wl,-R/usr/pkg/lib
-utils/CMakeFiles/usrp_x3xx_fpga_burner.dir/usrp_x3xx_fpga_burner.cpp.o
-utils/CMakeFiles/usrp_x3xx_fpga_burner.dir/cdecode.c.o -o
-utils/usrp_x3xx_fpga_burner lib/libuhd.so.003.007
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_date_time.so
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_filesystem.so
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_program_options.so
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_regex.so
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_system.so
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_thread.so
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_unit_test_framework.so
-/export/WRKOBJDIR/wip/uhd-git/work/.buildlink/lib/libboost_serialization.so
--lrt /usr/pkg/lib/liborc-0.4.so /usr/pkg/lib/libusb-1.0.so
--lpthread && :
-
-
-utils/CMakeFiles/usrp_x3xx_fpga_burner.dir/usrp_x3xx_fpga_burner.cpp.o:
-In function `extract_from_lvbitx(std::string,
-std::vector<char, std::allocator<char> >&)':
-
-usrp_x3xx_fpga_burner.cpp:(.text+0x17cb): undefined reference
-to `base64_init_decodestate(base64_decodestate*)'
-
-usrp_x3xx_fpga_burner.cpp:(.text+0x17e6): undefined reference
-to `base64_decode_block(char const*, unsigned long, char*,
-base64_decodestate*)' ninja: build stopped: subcommand failed.
diff --git a/uhd/buildlink3.mk b/uhd/buildlink3.mk
deleted file mode 100644
index bc23ec2..0000000
--- a/uhd/buildlink3.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# $NetBSD: buildlink3.mk,v 1.2 2014/09/07 03:33:52 makoto Exp $
-
-BUILDLINK_TREE+= uhd
-
-.if !defined(UHD_BUILDLINK3_MK)
-UHD_BUILDLINK3_MK:=
-
-BUILDLINK_API_DEPENDS.uhd+= uhd>=2.22
-BUILDLINK_PKGSRCDIR.uhd?= ../../wip/uhd
-.endif # UHD_BUILDLINK3_MK
-
-BUILDLINK_TREE+= -uhd
diff --git a/uhd/distinfo b/uhd/distinfo
deleted file mode 100644
index 9501cc2..0000000
--- a/uhd/distinfo
+++ /dev/null
@@ -1,6 +0,0 @@
-$NetBSD: distinfo,v 1.4 2014/10/04 12:40:17 makoto Exp $
-
-SHA1 (uhd/003_007_003_rc1.zip) = 7ccb0d562e4bd9d4dce073693974cbc180f63415
-RMD160 (uhd/003_007_003_rc1.zip) = 7fce33bafdcc80ce8f8b8c53233e25466cb4952d
-Size (uhd/003_007_003_rc1.zip) = 86689479 bytes
-SHA1 (patch-host_include_uhd_transport_nirio_nirio__driver__iface_h) = 2ba6c50f467515bfac9fe330572bb0154154a0ad
diff --git a/uhd/options.mk b/uhd/options.mk
deleted file mode 100644
index 467272e..0000000
--- a/uhd/options.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# $NetBSD: options.mk,v 1.3 2014/09/08 04:29:33 makoto Exp $
-### Set options
-PKG_OPTIONS_VAR= PKG_OPTIONS.uhd
-PKG_SUPPORTED_OPTIONS= doxygen manual
-PKG_SUGGESTED_OPTIONS= doxygen manual
-
-.include "../../mk/bsd.options.mk"
-
-.if !empty(PKG_OPTIONS:Mdoxygen)
-DEPENDS+= doxygen-[0-9]*:../../devel/doxygen
-PLIST_SRC+= ${PKGDIR}/PLIST.doxygen
-.endif
-
-.if !empty(PKG_OPTIONS:Mmanual)
-BUILD_DEPENDS+= ${PYPKGPREFIX}-docutils-[0-9]*:../../textproc/py-docutils
-PLIST_SRC+= ${PKGDIR}/PLIST.manual
-.endif
diff --git a/uhd/patches/patch-host_include_uhd_transport_nirio_nirio__driver__iface_h b/uhd/patches/patch-host_include_uhd_transport_nirio_nirio__driver__iface_h
deleted file mode 100644
index ff37448..0000000
--- a/uhd/patches/patch-host_include_uhd_transport_nirio_nirio__driver__iface_h
+++ /dev/null
@@ -1,24 +0,0 @@
-$NetBSD: patch-host_include_uhd_transport_nirio_nirio__driver__iface_h,v 1.1 2014/09/06 05:23:28 makoto Exp $
-
-To avoid asking IOKit/IOKit.h
-
---- host/include/uhd/transport/nirio/nirio_driver_iface.h
-+++ include/uhd/transport/nirio/nirio_driver_iface.h
-@@ -28,7 +28,7 @@
- #pragma warning(disable:4201) // nonstandard extension used : nameless struct/union
- #include <WinIoCtl.h>
- #pragma warning(default:4201)
--#elif !defined(UHD_PLATFORM_LINUX)
-+#elif !defined(UHD_PLATFORM_LINUX) && !defined(__NetBSD__) && !defined(__FreeBSD__) && !defined(__DragonFly__)
- #include <IOKit/IOKitLib.h>
- #endif
-
-@@ -441,7 +441,7 @@ static inline void init_syncop_out_params(nirio_syncop_out_params_t& param, void
-
-
- //Device handle definition
--#if defined(UHD_PLATFORM_LINUX)
-+#if defined(UHD_PLATFORM_LINUX) || defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
- typedef int rio_dev_handle_t;
- #elif defined(UHD_PLATFORM_WIN32)
- typedef HANDLE rio_dev_handle_t;
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